Methodical testing of Control Logic board - part I - movements

PUTTING THE DRIVE INTO READY STATUS AS PRE-THREADED TAPE

It is possible to thread tape manually through the machine and onto the take-up reel, then press the Load/Rewind button. This should advance the state machine to the DUMP state where the two reels rotate to feed tape into the vacuum columns. I set the BOT and EOT photocell inputs to the state if a tape were blocking the path, pushed the L/Rew button and saw the machine enter DUMP for 2.5 seconds.

Once the tape loops are sitting in the middle between the sets of photocells, the IN-LIMIT signal is generated which stops the load process and allows the drive to be made ready by pushing the START button. This should mark the drive as online and ready. It would then accept commands for movement.

Accomplishing this requires a bit of dexterity. IN-LIMIT must be off when the L/REW button is pushed, but after a couple of seconds when it goes into DUMP state, IN-LIMIT must be made ready.

To simulate the START button, I brought the input single low and then the circuit logic indicated my drive was online and that the READY lamp would be lit. At this point, it is primed for movement.

However, when I looked at the movement status outputs, the board was still commanding reverse, as it was still seeking the BOT tape. I had the signal active, but the logic for finding this requires that EOT be off at the same time. I tried to drop the EOT signal while leaving BOT activated.

This worked! The drive was still READY but the reverse movement stopped, the brakes were put on and it sat waiting for commands.

DRIVING VARIOUS MOVEMENTS ON THE DRIVE

The controller for the tape drives can issue commands to move forward, move in reverse, rewind, and unload by asserting input pins to this board. The action should continue as long as the command is asserted. In the reverse direction, it may be stopped by the BOT signal unless I deactivate it.

It took a couple of tries to get all the input signals hooked up and timed as needed to set up the drive as ready. That allowed me to reliably set up the motion tests below. While doing that, I found that any reverse movement was blocked by the brake on latch. I had suspected it was due to a bad 96L02 chip, but I see that the latch is being forced to reset by a bad NOR gate.

Chip U4B, a 74LS02 quad NOR gate, has pins 11 and 12 low (appropriately) but the output is also low, not high. Unless I could find a short somewhere on the board, then I had a bad chip. I flipped the board, inspected and did some basic beeping. It turned out to be a shorted input on a different chip, one which I had to replace and documented in a prior post. That was repaired.

I moved on to a more methodical checkout of the board, to verify the sanity of outputs, toggling the machine to various forward, reverse, rewind and other conditions, and stepping the loader state machine from REST until the drive goes ready.OFFLINE TESTING MODE

In addition, if the drive is not online, a pushbutton can enable the internal movement tester on the board. It can then move the tape forward and backward by pressing other buttons on the board. To accomplish this, I have to go through all the steps to ready the drive EXCEPT for the ON-LINE signal from the Start button.

Then, a pushbutton on the board will set the board into tester mode. First I verified that it accepted the tester mode push, then used the two directional pushbuttons to validate movement was being requested of the capstan logic.

This worked great - the tester drove the forward and reverse direction command outputs that control the capstan pre-amplifier. I didn't spot the forward command driving motion but after tracing through the chain of logic gates I found another gate whose output should be on but it wasn't.

It was one of the 74LS08PC quad AND chips, although drawn as an inverted OR. Trouble is, an OR of inverted inputs is not the same as an AND. They SHOULD have drawn it as an NOR of inverted inputs since that gives the same truth table.

Surprised it was misdrawn, I looked at other places where these AND chips were used to see how they drew them and found another place where they misrepresented it in the schematic as an OR or inverted inputs.

No wonder the chip output didn't agree with the inputs and the schematic symbol! It was working properly, thus my problem is in a different place than this gate.

AND gate on right side is incorrectly drawn as OR

When either of the inputs to the gate on the right above is low, it will drive the output low (thus should be drawn as a NOR with inverted inputs). That is the state I am seeing, which blocks the cyclic forward signals from the on-board tester.

The input 01 is high, since it is the notQ output of the rewind flipflop and we are not in a rewind. However, input 02 is low, driving the output low. The latch on the left is on, so the Q output (pin 5) is high. This drives the inverter output low(pin 15) which should cut off the transistor and make my NOR input 02 pull up to high.

In fact, regardless of whether the latch on the left is on or off, input 2 to the rightmost gate is always low. I have to zero in on those components and determine what has failed or is wrong with my test setup.

Transistor inverter

It is a pretty simple circuit - the gate of the transistor is pulled up to +5V with a resistor and then coupled through a diode to an open collector inverter (ULN2003) which either lets the gate float up at 5V or pulls it down to about ,6V, the voltage drop across the diode.

That means the transistor will be conducting in either case, pulling the output down. I don't see how this could switch off unless there is an applied voltage below ground level on the left side of the diode. After some research by my friend Ken, we discovered that this circuit counts on the diode voltage drop being around .45V, less than the .6 cutoff of the 2N2222 transistor. Not the best circuit in the world but it should be working.

Whether the input to the left inverter is high or low, the transistor remained conducting, pulling the circuit output low. I snipped the diode out of the circuit expecting that I would see +5 on the gate side, but it was near zero volts. We might have faults in an open R51 however it measures correctly. We might have a fault in C20 or in Q6.

Believing that a blown transistor is more likely, I removed it from the circuit and measured the voltages in the remaining components. All was as expected now, with both R50 and R51 showing +5V on both leads, while C20 had +5 and 0 on its two ends proving it wasn't shorted.

I grabbed a substitute PN2222 transistor and soldered it into place. It wasn't the same small round can format, but I was fine with the black plastic shape since it sat low to the board. After it was installed the malfunction began again.

Bad analysis on my part. I believe I have zeroed in on the cause and it is a fault in the left hand inverter. This is a darlington pair of transistors, acting as an open collector inverter. When the input pin is set to low the inverter does nothing and the circuit I am debugging will sit with the transistor conducting to produce a low output.

When the input pin of the inverter is set to high, the transistor pair should pull current to ground through the rest of my circuit, lowering the gate of my circuit until it turns off and the output becomes high. It is difficult to verify what is happening since the main action of this inverter is to be a current drain - a VOM isn't terribly enlightening.

What I chose to do was to apply a ground wire to the output of the inverter. That won't hurt the darlington pair at all, but will test the behavior of the rest of my circuit assuming the inverter properly pulls the output down near ground. I was pleased to see that the circuit being debugged would go high in this case. It appears the fault is in the darlington pair inverter.

The obvious next step is to remove the ULN2003 and replace it with a good one, but as a test of my theory, I can breadboard another ULN2003 chip and hook its output in parallel with the bad inverter. Applying a high signal to my breadboarded chip should produce the desired current drain and hopefully cause my overall circuit to operate properly.

Immediate snag - can't find another ULN2003 in my stock. I have to wait until Saturday evening to get the new chip, perform my test and potentially replace the bad chip.

Bad chip that I had already replaced - 74LS08PC

TRACING A DIFFERENT PROBLEM

I found my 'ready to move' latch on the control board being forced to reset but as I traced the signal back I discovered that it was due to a NOR gate U4G producing a low output with two low inputs. Rather than immediately pulling that chip, I looked for any evidence that the traces were being shorted to ground.

This NOR gate output hooks to two other chips, one of them is U2J that I had previously double replaced (first incorrectly and then to put in the right NOR chip). I looked very closely at the traces to see if my desoldering and resoldering had somehow shorted the trace to another one, but didn't spot anything.

Based on a hunch, I snipped the lead for pin 12 of U2J chip from the board and bent the leg up. It was still reporting a short to ground! That means I have a bad 74LS08PC chip and would need to replace this chip site for a third time. I fired up the board with that leg lifted to verify that the U4G NOR gate is giving proper outputs.

This time, I installed a DIP socket so that I never have to resolder again as the traces are quite funky after all the desoldering. That allowed me to beep out the connectivity and install rework wires before I had a chip in place.

I found that pins 1 and 6 should be connected but the trace soldered incorrectly onto pin 2. This required a small bit of rework under the board beneath the socket. I then had to address some misrouting of traces for pins 11 and 12, but once it was repaired, the board was ready to have the hopefully working 74LS08PC chip inserted into the socket.

Single shot chip takes a dive - not so amusing distraction

MYSTERY FAILURE OF CLOCK TRIGGER CIRCUIT

The following circuit is given a set of pulses with a 60Hz rate, which should produce properly shaped on and off times to feed into a 'ready for movement' latch elsewhere on the board. I found an unvarying high clock signal on the 'ready for movement' latch and traced back through the circuit to understand where it was failing.

Clock shaping circuit

The input pin 4 on the left receives the 60Hz square wave signal. It should produce an inverted clock out of pin 9 on the right, but all I had was a steady logic level. First up I checked the existence of +5 on pin 16 and ground on pin 8. Next I verified the input was good on pin 4.

The two reset pins, 3 and 13, should be held high and have continuity to pin 5. Check. All other components, two capacitors and two resistors, were wired properly. . I decided to beep out the entire circuit, just to be sure the diagram was accurate since I found the added 1K resistor R68 during prior explorations of the board. Unfortunately, the conclusion is that the 96L02 chip has failed. Valid +5V on pin 5 and square wave input on pin 4, but no action on pins 1, 2 or the outputs 6 and 7.

Time to buy a replacement, however there are none at Anchor or the usual online retails like Digikey and Mouser. Ebay purchase will add at least a week delay, thus hoping to find a faster alternative I started hunting other retailers. I found Vetco in Washington state who sold me one with USPS flat rate envelope delivery which ought to get it to me later this week

Putting the correct 74LS08PC chips onto the board

FIXING THE CLOGGED HEADS OF MY HAKKO FR300 DESOLDERING GUN

My desoldering gun sucks the solder through a fine opening in the tip, but it can easily get clogged. The tips I use, 0.8mm and 1mm openings, come with ramrods to help clean them but once a serious clog develops, the rod will no longer work.

The problem tends to happen with a bit of debris such as a chip lead is sucked into the tip. When solder forms around it and hardens, we no longer have sufficient suction to clear the solder out of the PCB holes.

I ordered two new tips but also bought a hand drill set with small drill bits that I can use to clear out the two original tips. When these arrived, I was able to drill out the 1.0mm tip but did install the new 1mm tip to use removing the wrong chips.

REPLACEMENT OF THE FIVE MISIDENTIFIED CHIPS

Removing the old chips was the time consuming part. Putting new chips into the board and soldering was quick. I was fortunate to have dozens of 74LS08PC (quad AND gate) chips on hand. Due to the two chip removals, I had some pads that had lifted from the board - typically where the pin has the trace on the top of the board but uses a pad on the bottom as an anchor. I decided to attempt to touch up the top side of the pins in question.

BEEPING TO VALIDATE CONNECTIVITY

Because of the potential for broken connectivity due to the lifted pads and other issues in the rework locations, I beeped all the connections from the 90 pins affected, ensuring that I still had connectivity after my second serial repair in this spot.

I needed 2 extra short jumpers in addition to the one that was previously added to U6J. I have full connectivity so the replacement back to the proper chips is complete.

TESTING RESUMES

My initial test was to see that the machine powers up in the REST state and with the BACKWRAP signal off (high). A push of the Load/Rewind button should advance the load state machine to WAIT state and force BACKWRAP to ground. If these worked, it suggested that I had a board in decent condition.

Indeed, BACKWRAP is now high, which means inactive, when the board powers up or is reset. When I 'pushed' the Load/Rewind button, I saw the state machine advance from REST to WAIT, which should have lowered BACKWRAP, but it didn't.

I looked at the logic involved and found that the WAIT state is only one of the three conditions that must be correct in order to take BACKWRAP to ground. The other two are CART-PRESENT, since when the operator uses a tape with an autothreading band the state machine does not back wrap. The third is TAPE-PRESENT, a signal that is active if either of the phototransistors that look at Beginning of Tape (BOT) and End of Tape (EOT) is switched on.

Since I have no connection to the phototransistor board, the default state is the same as having both light sources blocked. The drive interprets that as an attempt to do a Load/Rewind after power-up with tape already threaded through the drive. In that case, we don't want to try threading.

I wired a pullup resistor to the inputs for BOT and EOT, which eliminated the false detection of TAPE-PRESENT. This left the logic primed so that when the state machine does to WAIT, the BACKWRAP should drop to ground level. That is indeed what happens!

It is time for me to step back and map out a comprehensive test plan, first verifying the default power-up states of all the output signals. Next I can test the major functions of the control logic:

• Powering up while tape is 'in the tape path', then readying the drive
• Driving forward both via input pin and by the test buttons on the board
• Repeating with reverse, both by test button and input pin
• Verifying operation of rewind command from input pin
• Trying Unload button and watching the behavior
• Trying Load/Rewind on ready drive, watching behavior
• Stepping through the load sequence for non-autothread cartridge
• Stepping through the load sequence for autothread cartridge
• Stepping through the load sequence for mini-reel

In the load sequence tests, I want to test both successful attempts and time-outs to insure that the state machine is working properly. This will involve simulating changes in input pins at specified times. 

Beeping out the rest of the Control Logic board to verify traces and schematic, found a big problem

MISSING AND BONUS COMPONENTS VERSUS SCHEMATIC

I spent some time reconciling the components found on the PCB and in the schematics. Once I had my spreadsheet in good shape I was able to quickly locate parts for beeping out connections.

I discovered quite a few that were on the schematic, in the range of R82 to R88 along with associated capacitors from C64 to C67 that were not on my board. Where these parts were shown on the schematic, straight connections existed.

Two resistors, R80 and R81, were added onto my board as a rework in an unprofessional style that led me to believe that the prior owner added these on their own. Another component R77 on the PCB was found to be in line with a connection that is a straight wire on the schematic, thus it was deleted in later boards.

R80 added under U1B

R81 added with tubing and loose resistor

I also found that resistor R76 was not on the schematic and the board has a 0 ohm resistor installed, thus this was a rework to the schematic version of the circuit from an earlier version of the board.

TRUDGING ALONG BEEPING EVERY PIN TO ITS OTHER END(S)

After another two hours I had the rest of schematic page 2 verified. Perhaps I am speeding up a bit, based on a new method where I first extract all the tests from the schematic as a list of connections; a made-up example would be U4A 4 - U2A 2 - U5E 10- R22. When I had a full page of connections listed, I could swing through with the continuity tester and check off each as it passed. Thus I projected that my average speed for the remaining four would be 3 hours per page.

After only another hour I had page 1 complete - quite a speedup. Page 3 went a bit slower but by the time I reached the end of that page, without having found any broken traces, my confidence in the basic integrity of the board had grown substantially. I could still have bad ICs, since I have already found seven of them, but the board continuity is sound. I had a dinner appointment thus work on pages 4 and 5 started the next afternoon.

I wrapped up work on page 5, finding no missing connections to components. It was time to hook this back up and begin checking out the various circuits as I introduced inputs.

ODDBALL MEASUREMENT OF OPEN COLLECTOR INVERTER OUTPUT

One part of the logic that controls the BACKWRAP output signal is an open collector inverter, pulled up to +5V by a 10K resistor, whose output is feeding two AND gate inputs. When I measure the resistance on the inverter output pin U6E 10, I see 5K to up to +5V but the pullup resistor R79 is 10K.

Portion of the BACKWRAP signal circuit

I lifted the pullup resistor from the circuit and measured open circuit. I measured the lifted resistor as 10K. When I soldered it back in place, the measurement on U6E pin 10 went back to 5K ohms. There would be no resistor in the output circuit of U6E but perhaps some interaction with the AND gate inputs is giving me the reading.

THAT 'DOH' MOMENT

Look carefully at the schematic excerpt above, at gate U2J. I read that as 74LS00 and installed one in the board, but in fact the gate is a dual input AND, while the 74LS00 is a dual input NAND. The correct part number is 74LS08N.

After I checked all the other chips I replaced with74LS00, looking at the schematic carefully, I knew that the five such chips I declared bad based on the boolean logic behavior were in fact supposed to be AND gates.

I will remove all five (again) and populate them with the correct chip. To be safe, after the soldering I have to beep out all connections from the 70 pins, but that will be pretty quick compared to the comprehensive scan I just finished.

Seventh chip replaced, testing resumes at a snail's pace

After replacing the bad 74LS05N chip, I repeated the test to verify that the BACKWRAP output signal would float high if hooked to a suitable pull-up resistor, while the machine was in the idle (REST) state. That did not happen, and it appeared to be the fault of the the same gate. It had a low input, open collector inverter gate with a pullup resistor on the output. This should result in a high output.

Suspiciously, the resistance from the output pin to +5V was measured as 5K but the resistor is marked 10K. This leads me to think that a trace is shorted to some other trace with a 10K resistor as well, producing the reading I found. If the other trace is another open collector output that is pulled to ground, it would match the behavior I saw.

I have been testing connectivity to every pin as I solder in the replacement chips, but that won't show me shorts to additional traces. I will have to find it by trial and error, coupled with hints from the schematics such as OC gates with 10K pullup resistors.

The board has 90 chips, quite a few capacitors and so forth, plus a ton of resistors. The location of the resistor on the PCB is almost random, often nowhere near the chips it is connected to. Further, the numbers hop around randomly by location. It forces me to carefully search the board for each resistor I want to locate, wasting significant time.

To make this easier, I decided to use a high res picture of the board in order to build a spreadsheet for all the components. The chips are labeled strictly by their physical location on the board, but nothing else is so conveniently numbered. The chip rows are numbered 1 to 6 and the columns are labeled A through J.

Therefore I will apply that location scheme to my spreadsheet. Parts below row 1 of the chips are in component row 1, parts between rows 1 and 2 are in component row 2, and component row 7 is for parts above the top row of chips. When a part is to the side of a column letter, I will use the letter to the left of the part. Any part to the left of the J column will be marked as component row K.

My first pass looked at components on the board, placing them in their site by the scheme above. The second pass covered the five pages of the schematic, identifying each component with its page number and approximate spot on the page. I used a Left-Center-Right and Top-Middle-Bottom grid for the schematic locations.

I was left with a few components I could see on the board but not on the schematic. Other components were drawn on the schematic but no visible on the board. I suspect a version mismatch between the board and the schematic. The first signal I traced out which had components on the schematic but not on the board was an input line that had a series resistor and capacitor to ground, intended as a debouncer, but beeping the circuit showed that the input line went directly to the gate. Thus, I will have to contend with the documentation mismatch.

I began a very tedious process of beeping out all the connections between the chips and to the input/output pads. With 90 chips having an average of 14 pins, plus a couple hundred non-chip components on the board, there was a lot of testing to complete. In many cases, one of the pins is fed or leads to a part on a different schematic page, so flipping and recording of source/destination is necessary.

I began randomly with schematic page 2. I realized that once I had tested all the off-page connections from this page, they were tested whenever a signal ran from another page back to 2. This will speed up my page flipping as I advance through more completed pages.

More discrepancies between the schematic and the board arose. For example, when the loading state machine enters the Wrap state, a timer was triggered that on the schematic had a 15K resistor and 100uf capacitor, but on the board I found a 470K resistor and 2.8 uf capacitor. Those combinations are about the same RC constant although with very different currents during charging.

It took me about two hours to complete 1/3 of a schematic page, thus a linear extrapolation would put the remainder of the task at 28 hours work. Some of the pages are sparser and there will be the speedup effect dealing with off-page connections to pages I have already completed, but a conservative estimate is another 2 or 3 days elapsed time.

Continuing debug of control logic board

I proceeded to push the L/Rew button by temporarily grounding the appropriate input, while watching the state machine for an advance to WAIT before timing out and ending at LD CHECK state. Initially it didn't work, which I traced to the reset of the state machine forced by leaving the IN-LIM-1G0 input high.

This signals that the tape is in the vacuum columns between the low and high points. Once the tape has loaded like that, the load sequence is over and reset is forced. I added a wire to pull it to ground which then allowed the L/REW pushbutton to advanced the state machine from REST to WAIT.  It sat there until the timer expired, then jumped forward to load check state.

In between each such test, I 'push' the Reset button by grounding its input, to restore the state machine to REST and to clear all errors. This process worked fine. I won't document this step any further but will reset between every test attempt.

I also checked that the appropriate outputs such as BACKWRAP were activated while in WAIT. This is an open collector output, thus I had to pull it up with a resistor before probing the output pin. When in the idle (REST) position, this signal is pulled high but upon entering WAIT it is pulled low.

Another initial failure, as the signal was always on (pulled low). I traced through the signals that generate this output to see whether there was another input I needed to force low or high. I analyzed the gates to figure out what would make the output normally high but drop low while in WAIT.

The key signals and their required state, in order for the BACKWRAP to be triggered only in the WAIT state, are:

• CRT-PRS-0X0 should be high, indicating that an autoload cartridge is not present
• TAPE-PRS-1G1 should be low, indicating that the tape is not in the path near the tape head
• P-EOT-SW-1S1 should be low, indicating that the end of tape is not near the entry slot
• WRAP-1+2-1G0 should be low since the state machine is in REST or WAIT
• HUB-V-SW-0S2 should be high indicating that tape is not wound around the take-up reel
• THRD-1+2-1G0 should be low since the state machine is in REST or WAIT

With the conditions above satisfied, the output of the BACKWRAP signal is high (logically off) until the WAIT state signal goes active which drops the output to low to signal to the reel motor preamp board that it should slowly rotate the supply reel counter-clockwise.

I fired up the board, left it in the default REST state and probed all the signals above to determine which ones were incorrect. I immediately found another bad chip (U6E), a 74LS05N hex open collector inverter. When I measured the resistance of the output to +5 (pull-up resistor in the circuit), I got about 500 ohms but the resistor in question was 10K.

I looked at the pullup values of the other five inverter outputs, then calculated the equivalent parallel resistance if all six outputs were shorted together - 556 ohms. I removed the chip from the board, confirming that all outputs were shorted to ground with the chip unconnected. Time to replace it with a good chip and hope that I don't have too many other blown chips waiting to pop their heads up as I check out the logic.

Replacing defective chips on the drive B Control Logic board

FINISHING SOME CHIP TESTING

I did look at the outputs of the 96L02 since it has both Q and Qnot, which must be different. The LM311 op amps I tested by swinging the input voltage and watching the output. The open collector 7416s drove off board circuits and had no pullup resistors, so I added it to the probe and performed the irrational combination test. The only chips for which I had no test at all were the NE555 timers and the ULS2003 which drove indicator lamps and thus was open collector too.

DEFERRING THE DECISION

I began to remove the bad chips, letting the effort involved determine whether I will continue to take all of them off and replace them. The method I used makes use of a vacuum desoldering station, a soldering station and clipping away the chip body.

I snipped off all 14 leads up at the chip body, removing the IC itself. This left me with short metal pins that were soldered into the board. I attached forceps to each pin, dangling on the underside of the board, while I applied heat on the top side of the board. The goal is to have the pin pulled out cleanly.

Once all the pins were removed I couild use the Hakko vacuum desolderer with a small tip size to suck the solder out of the holes. That gave me six chip sites with all the holes clean and ready for the new chip. My decision was made - time to replace the chips with new ones and continue testing.

VERIFYING THE SUBSTITUTE CHIPS ONCE SOLDERED TO THE BOARD

I have a supply of all chips on hand, so I began merrily installing and soldering the 84 pins to the board. Before I power up a board where I have replaced chips, I do some continuity testing to ensure that the pins of the chips are hooked into the circuit per the schematic. This is particularly important with the visible desoldering heat damage at one location.

New chip in place - some heat damage to board on lower right

Resoldered pins on the bottom of the board

For the 74LS14 chip, I had to check the six inverters, testing that the input came from the other components on the board and that the output went to its intended destination component. I found a problem with one of the inverters - the input pin was not connected to the resistors and capacitor as it should be. The solution is a small wire from pin 13 of the chip to the resistor.

The other five chips, each a 74LS00N, have three three-input NAND gates apiece. This means I needed to verify connectivity of 60 pins, 12 per chip. Fortunately, all checked out fine, so only one rework wire needed.

The final complication to sort out was existing rework on the board, consisting of several small blue wires that connect to various chip pins and other components. I wasn't sure what this was doing, so I recorded all the connections, located the chips on the schematic, and drew out the purpose of the rework.

Part of the rework I found on the board

Once I began tracing it out, I found that these were replicating connections shown in the schematic. That suggests that these were added to compensate for broken traces that occurred at some prior time. Another sign that this was an old and perhaps scrapped board stuffed into the cage after the shipping damage.

INDUCTOR REPLACEMENT NEEDS REPLACEMENT

The inductor I bought from Anchor, a 100uh axial, has almost 5 ohm resistance. Since this is a choke on the 5V input to the board it is going to drop a fair amount of voltage - for example if the board draws only 100ma then the inductor will cut the 5V supply to 4.5V at the chips.

Digikey had a replacement that can handle up to 1.3A with just 0.2 ohms resistance - a much better component for the board. It should arrive in a few days and I will swap it for the inadequate one.

Check all ICs on Control Logic board for irrational combinations

IRRATIONAL COMBINATIONS

Each logic gate type has defined behavior. The simple combinatorial gates in particular have easily checked conditions. The inverter must have opposite states on the input and output. AND gates must obey the logic equation, only having a positive output if all inputs are positive. Of the 15 types of chips on the board, eleven fit this category where some combinations of states represent a failed chip.

The NE555 timer chips have defined behaviors but no irrational combinations to check. The LM311 op amps do not have illogical combinations but I can check their behavior by varying the input signals thus they can be separately checked. The

CHECKING ALMOST FIFTY CHIPS FOR IRRATIONAL COMBINATIONS

I printed the data sheets of all the possible irrational combinations so that I could perform the checks on the logic board. Previously I had pored over the five pages of schematics and built a list of the chip types at each of the 94 locations. Armed with this, I powered up the board and began stepping through all the chip tests.

I found quite a few bad chips. This board had previously had a missing inductor and a broken resistor, then I discovered a bad inverter chip which is why I thought I would do a scan for irrational combinations prior to replacing the inverter.

The final tally is five 74SL00 and one 74LS14 chips.

MY SUSPICIONS ABOUT DRIVE B

With this many chips bad, I suspect this is evidence of insurance fraud. The reason for my suspicion is the signs that this board failed in service on some other drive. With the high number of bad components, it would have been either sent for rework or scrapped.

However, since a shipper damaged the drive with a forklift, the entire drive would be written off by the insurance company and the unit scrapped. By rights, the intact boards inside belonged to the insurance company.

If an unscrupulous organization took the opportunity to swap out all the good boards, repopulating the card cage with bad cards, they would avoid the charges for the bad boards and obtain good spares from the drive that is now property of the insurance company.

Other explanations are possible so I can't be totally certain. When the drive fell backwards and bent its frame, perhaps the shock broke leads inside the IC packages. It is a very high number of chips to have damaged like this, but it is possible.

The five bad 74LS00 are all marked El Salvador, but the 74LS14 is not. Some of the good 74LS00 are also from El Salvador and that is the only source for all the 74LS00 chips. There may be a bond on the chip, as it was made in that factory, that is susceptible to shock, leading to a high failure rate. The fact that only 6 of the 84 chips failed and that five of them were this type, may support that theory.

As a counter theory, the board has pen ink marks on some pins of the chips, which likely occurred as a technician traced a path while debugging the board. Once they discovered that six chips were bad at a minimum, they likely tossed it in the scrap pile where it waited until a drive was damaged in transit.

PLANS FOR THE BOARD AND FOR DRIVE B

The major hassle in reworking these six chips is that I have to clear solder from 84 pins to remove them, then insert the replacement chip pins in the partially clogged holes. The cost of the chips is insignificant, it is the time and effort that looms large.

There is no guarantee that the chips which passed the irrational combination tests are working properly, only that they weren't provably bad like these six. Some other bonds may have failed or portions of the chip dies might be bad but not show up with the particular combination of inputs at idle.

Since I am doing this restoration for the hobby fun, having no purpose for the drives once they are running, I have to think a while about whether to proceed.

Chasing faults in second drive Control Logic board

HOW BACKWRAP SIGNAL IS GENERATED

Gates that produce the BACKWRAP signal

As we study the schematic above, it shows that the BACKWRAP signal is produced by both inputs to AND gate 215 being high. Essentially this is active in the WAIT state of the sequencer when the autoload cartridge is not detected, but can be broken by sensing the physical end of tape and by a few other error conditions.

VERIFYING THAT BACKWRAP IS ACTIVE

I set up the bad control logic board in the tape drive, with probes hooked up to pin 07, the BACKWRAP signal, as well as to one pin of the binary-decimal decoder chip that indicates whether the sequencer is in the WAIT state.

At power-up the sequencer should be at the REST state and therefore we should not be producing BACKWRAP. My tests showed that BACKWRAP was floating low and that the REST state was NOT active! At this point I need to do more debugging to figure out what is happening.

PREPARING TO TEST OUT OF THE MACHINE

I pushed on my 70 pin connector to the board in preparation for wiring up the power rails and beginning testing. I happened to check connectivity between the VCC pins of the TTL logic and the +5V input and immediately found my (first) problem. The choke inductor L1 that connects the +5V from the backplane to the rest of the board is missing!

100uh inductor goes here

I took a quick run to Anchor Electronics for the inductor, then soldered it onto the board. I took the time to wire up the power and input lines from the connector to the terminal strips I also bought. This gives me a 1x20 and 1x15 for each side to cover all 70 positions (eventually).

Initially I chose only 35 wires to solder, still a tedious task. Making matters worse, one of the pins broke off on the connector. I was able to tack solder that wire back, just in case I need to simulate the End of Tape (EOT) sensor input which is assigned to that pin number. .

With everything in place, I hauled out my triple power supply to provide the +5 and -12V DC voltages to the board. Another power supply provided 12.6VAC which let me fully power the board.

Most of the inputs have pull-up resistors on the board and depend on a sensor or switch connecting the line to ground in order to activate it. That is convenient because I could leave most lines unconnected and still get reasonable behavior.

BENCH CHECKOUT OF THE CONTROL LOGIC BOARD

First up was power application and a sanity check of the state of various outputs and internal gates. I wanted to ensure that none of the movement command outputs were active (low) and that the loading state machine was sitting at the REST state initially.

Indeed the state machine was at REST and none of the REV, FWD, WRAP and other movement oriented signals were active. However, when I 'pushed' the Load/Rewind button the sequence didn't advance. I looked at the circuitry that should trigger the step input to advance the load state machine.

I found that the logic asserts that the L/Rew pushbutton is active, so I traced back to see why this is happening. The switch itself activates to ground with the line pulled up to 5V when inactive. It passes through an inverter so that the low logic level of the active pushbutton turns into a high level for use to advance the state machine.

Both the input and the output of the inverter are at logic high level! Since the button isn't pushed, the input makes sense but the output should be low. I checked the operation when I grounded the input to simulate the pushbutton. The input to the inverter does move properly but the output is bad.

I decided to check the other inverters on that chip to see if there are any other gates in the chip showing incompatible logic levels. Indeed, the very next one I checked was also showing high-high so the chip is blown. I located another 74LS14 chip on the board and found that its gates had compatible values on the inputs and outputs.

Before I replace this one, I will do a sanity check on all the chips on the board, looking for illogical combinations of inputs and output. I would prefer to assess the scale of the problems on this board and identify if any other chips need replacing so I can do them all at the same time.

I need another trip to Anchor to pick up replacement chips for any that I don't have in stock.

Studying Control Logic to allow me to debug loading and repair second PCB

STATE OF THE CONTROL LOGIC PCBS

I have two boards, one from each of the two tape drives. One of them is clearly defective, because the supply reel will slowly rotate at power-up. The other is seemingly working, but I do have the problem that my drive won't autothread successfully nor dump and go ready successfully.

I would like to repair the bad board which is justification enough to study this board and debug it. But, it is possible that the other board is not working properly causing the loading faults, thus it would be great to debug that one as well.

APPROACH FOR DEBUGGING

I could attempt to record all the signals as the boards work while installed in the drive card cage. The other method I can use is to hook it up to a connector on the test bench and provide suitable input signals, thus verifying its behavior with full access to all component leads as well as the board connector signals.

This needs to be powered with +5V, +12V, -12V and 12VAC, thus I need my triple power supply and a separate AC source. The PCB connector is dual sided, 36 fingers per side. 53 of the fingers are used for inputs and outputs, another 13 for the power connections. Six are unused, but I need a convenient way to hook up to the 66 that are active.

Some will be permanently wired (power and steady input signals), some will be probed only to watch outputs, and the others will be variously toggled on and off to drive the logic board through its paces.
Pushbuttons command actions such as Load/Rewind, tape drive sensors report on the presence of vacuum, tape at various points, light at the BOT sensor and so forth. These need to be switched.

ANALYSIS OF CONTROL LOGIC

This board monitors the operator pushbuttons (e.g. Load/Rewind, Reset, and Unload) to perform the requested actions. It monitors the photosensors looking for the beginning of tape and end of tape markers and the sensor detecting that the take-up reel is almost empty of tape. It sees the vacuum and pressure switches that detect a auto-open cartridge, tape wrapped around the take-up hub, vacuum in the vacuum columns, and the end of the tape present near the entry throat to the tape path chamber.

A large potion of the logic is involved with the autoloading capability of the drive. This is centered on a state machine built with integrated circuits, not a controller or microprocessor chip. A binary to decimal decoder chip outputs one of eight valid states of the machine or has all turned off for the remaining inputs.

The state machine assumes each new value by a trigger signal. It is a line that is raised by combinatorial logic when one of the conditions occurs which should cause a state transition. As such, the circuitry is mainly asynchronous rather than clocked.

At power-on or when the Reset button is pressed, the flip flops are set to zero and the decoded state is 0 - the REST state. The first event that occurs to cause a clock to change the state is when the Load/Rewind button is pressed. This causes the decoder to output a 1 for the WAIT state.

The trigger signal to advance the state can be generated to kick off autoloading by the Load/Rewind button, but it also is generated by two classes of events. First, a physical sensor is activated, such as when the tape is detected wrapped around the take-up reel hub. Second, a timer goes off if the desired activity has not completed in the alloted time. .

In each of the states where some physical action has to occur, such as the two above, a 555 timer is set. The timer can be set to various durations, all multi-second. If the physical sensor is triggered before the timer pops the timer is reset and the state machine successfully advances.

The single 555 timer is used to provide several different time intervals by switching in resistors. Three transistors are used, switching in a 330K, 200K and 100K resistor respectively. The highest selects an 8.5s interval. In addition to three times using a single resistor, more than one can be switched in to produce additional durations.

Some logic on the board will drive the tape forward or in reverse, either momentarily while a test switch is pressed or in multisecond cycles driven by a pair of interlocked timers. This is for manual testing.

Commands either from the tape control unit or the test switches request the capstan to move tape forward or reverse. The control unit can simply move the tape or it can watch the data flowing from the read board or send data to the write board if it is performing a read or write. Rewind and Unload are two other commands that can come from the control unit or locally by button presses.

Each state of the autoloading sequencer commands different behaviors from the two reel motors and the capstan. For example, the BACKWRAP command rotates the supply reel counterclockwise until air pressure flips the end of the tape over the vacuum sensor hole near the entry to the tape path chamber. This is during the WAIT state.

After detecting the end of tape, the state machine advances to THRD-1 which asserts the WRAP command to cause the supply and takeup reels to both rotate clockwise. This feeds the tape into the tape path chamber, down through the head and out to feed onto the take-up reel.

Other logic on the board will control the rewind and unload processes, much simpler than the autoloading process thus only needing a few flipflops and not a state machine.

HINTS FOR WHERE TO LOOK FIRST TO DEBUG THE BROKEN CONTROL BOARD

The bad behavior manifested by the broken control logic board is counterclockwise rotation of the supply reel immediately at power up. This would be caused by the BACKWRAP command being asserted even though the autoload state machine is still at the idle REST state.

I can probe the state of some pins on the backplane while the broken board is installed. After I verify that BACKWRAP is asserted, I can check that the state machine is in the REST state. If so, the problem is in a few gates that generate BACKWRAP. If not, the state machine logic is not working properly. Either way, I can dive in from there.

Collecting data on the failure to autoload tapes or dump into the vacuum columns

WATCHING AN AUTOLOAD ATTEMPT WITH ACRYLIC COVER

This was quite interesting to watch. I attempted this about five times, all unsuccessful. The first was the most successful try.

The tape did indeed thread itself around the perimeter and out to the take-up reel hub but it stopped threading too early. It should have fed more tape and wound it a few times around the hub before switching on vacuum and attempting to dump into the columns.

The remaining attempts never got that far. Once the supply reel refused to turn at all. The other times it fed in part way then gave up and rewound onto the supply reel a few seconds.

WATCHING AN ATTEMPT TO DUMP A MANUALLY THREADED TAPE

I began with the tape manually threaded through the machine and around the take-up reel, pushing load with my acrylic cover held in place. In fact, the tape did dump down and form the two loops midway into their vacuum columns, but the machine then recognized a load check and dropped vacuum. I need to see what other failures can lead to the load check symptom, as my problem may be elsewhere.

IMPLICATIONS OF WHAT I WATCHED

First, I was concerned about the one case where the supply reel didn't move at all. It has worked reliably every other time but it might hint at some unresolved problem.

The time it threaded successfully we either ran out of time or didn't set sufficient time to wind the tape around the hub a few times. I had to investigate this.

Using my scope I watched the test point that shows me timer intervals. The 5.5s timer was measured at 5.0s, a bit short but somehow this can't be the whole story. Perhaps the turning speed of the reels is too low, or some key signal is not being processed. For example, when the tape begins to thread into the path, it has only 3.5 seconds on a timer.

During that time, the BOT sensor that looks for the bright start of tape reflector should go dark as the tape passes that point. This resets the timer to 5.5s which ought to mean that we have at least that amount plus whatever time was used to darken the BOT photocell.

The problem is that I don't really know what is normal. Is the reel turning too slowly? Is the time interval a bit too short and causing the problem? Is there another defect on the control board or with the capstan that I haven't detected yet?

Drilling down into failure of drive A 'dump' of tape into the vacuum columns

LOGIC ANALYZER SET UP CHANGED SLIGHTLY

Since the visual evidence showed that the failure is occuring in the upper vacuum chamber, fed by the supply reel, I can remove the signal leads from the lower chamber and instead use those leads to monitor the pressure/vacuum differential switch signals that trigger changes in the loading state machine.

I believe that the switch recording vacuum in the chambers will activate (go low) at the start of the dump sequence. This is where the supply reel will move clockwise to allow the tape across the mouth of the upper vacuum chamber to be sucked downward.

The loop of tape in the chamber should pass across four photocells near the top of the chamber, the reel should stop at that point and the tape loop should NOT pass across the other four photocells at the bottom of the column.

RESULT OF ATTEMPT TO LOAD MANUALLY THREADED TAPE

I was not happy with the reliability of the data I was collecting. Depending on where I push on the acrylic cover, I get different failure results. In one case the tape edge folded over instead of sliding down the column in a loop. I think the plate flexes enough that if I push within a column it narrows below the width of tape.

The logic analyzer did record signals but I never saw the vacuum signal go low, in spite of the fact that something triggered the capture. Without seeing the signal go down, I can't trust what I am seeing. Either there is some change I need to make to the logic analyzer software in the Analog Discovery or I have to move over to my full size dedicated analyzer.

Gleaning hints for what is transpiring behind the metal cover of the Telex 8020 tape path

LOADING PROBLEMS

Both of my drives are failing when attempting an autoload. When I hand thread the tape through the path and onto the take-up reel, it fails to dump the tape into the vacuum columns properly.

In both cases, I am not sure exactly where problems are arising because the tape path and vacuum columns are covered by a metal plate. The Telex repair people had a clear plastic plate they could substitute for the metal one, thus observing any defects in loading.

INTERIM APPROACH DEVISED WHILE WAITING FOR CLEAR PLASTIC COVER

I designed a clear plastic plate and sent it out for fabrication yesterday, but won't have it back for about a week. In the interim, I am looking for clues I can gather to help narrow down the area where the load process is going wrong.

If I can access signals that tell me the location of the tape, particularly in the two vacuum columns, it might tell me what kind of failure is occuring. The tape might not enter the column at all, or it might bottom out without the servo loop properly controlling the reels.

I looked at the schematics and was pleased to see that all the signals I want to view are conveniently present on J1 near the bottom of the logic card backplane. Each vacuum column has eight LED-photocell combinations, four at the top of the column and four at the bottom. These signal the current position of the tape column.

The servo mechanism for each tape reel, while in dump or run mode, should turn the reel motor at increasingly high rates as the tape loop moves through the four photocell locations - turning in one direction, to feed in more tape when the loop is at the top of the column, and in the other direction to pull some out if the loop is approaching the bottom.

I set up my Digilent Analog Discovery as a logic analyzer, capturing the state of the sixteen signals over time. Most jacks hooked to the logic cage have a set of wire-wrap pins sticking out for convenient access to the signals on various socket pins. Not so with J1, unfortunately.

I then had to seek an alternate way of capturing the signal. If a signal arrives on one of the sockets on the back of the logic cage, I assumed it must be connected to at least one of the backplane pins behind the PCBs. The only other routing would be socket to socket, bypassing the logic cage.

I found the signals on card slot 4, pins 23, 25, 27, 29, 31, 33, 35, 37. 39. 41, 43, 45, 47, 49, 51 and 53. Nicely sequential and easy to wire up. With the Analog Discovery cable wired up, I brought out the device and hooked it to my laptop, where I configured it as a 16 channel logic analyzer. With that done, I powered up the tape drive and then plugged in the cable to the device.

THINKING ABOUT AUTOLOADING FAILURE

The autoloader depends on air pressure at a number of points to guide the tape around the perimeter of the tape patch and out toward the take-up reel. If any of those are not producing flow, or have inadequate flow, the tape will droop into the upper vacuum column which is what I presume is occuring.

I know there is enough flow to separate the end of the tape on the reel and to blow it up onto the PEOT sensor that detects the end of the tape covering a vacuum port. There also must be air flow inside the chamber so that as the end of the tape enters the covered area it is blown upwards towards the top edge.

Once the tape is pushed along the top edge to the top-left corner, more air pressure should drive it downward through the tape head. Finally, at the bottom left there is pressure to force the tape rightward towards the exit slot where it continues to the take-up reel.

The process of loading spins the supply reel until the end of tape is sensed at PEOT, then it reverses and threads the tape which should be forced by air pressure across the top, left and bottom edges of the tape path. After the tape exits the bottom slot and reaches the take-up reel hub, vacuum holes in the hub grab the end of the tape and a sensor switch detects the Hub Vacuum condition.

The tape winds a bit more around the take-up reel before a timer expires and begins the dump sequence. The supply reel feeds tape in and the take-up reel unwinds some tape. The solenoid based valve should have switched to provide full vacuum to the two vacuum columns, so that when tape is released by the two reels it is sucked down into the upper vacuum column and sucked up into the lower column.

A servo loop between the detected tape position, using photosensors, and the reel motor will feed out or pull back some take to each reel to maintain the tape loop in the middle zone of each vacuum column. When the tape is in position and a timer expires, the drive begins to seek forward looking for the BOT reflective spot that signals the beginning of tape. It stops the motors and illuminates the Load Point lamp. This completes an autoload sequence.

With tape being manually threaded through the path and wound on the take-up reel, the drive is smart enough to detect the Hub Vacuum condition and switch immediately into the dump state. It should switch on vacuum to the chambers and cause each reel motor to feed out some tape until the loops are in the middles of the two chambers.

While the drive currently won't complete the self-threading, it used to. Back then, it would fail in the dump state. This may be the same failure that occurs when I pre-thread the tape, or a different one.

COVER ARRIVES - NOT PERFECT BUT WORKS FOR MY PURPOSE

The picture I took and used to trace out the outline of the metal cover was obviously photographed at an angle and suffered parallax errors. The resulting cover is close but is particularly out of alignment near the top.

Acrylic cover over tape path and vacuum columns

Fortunately, it will fit over the tape path and vacuum columns permitting me to do some testing. The misaligned holes near the top may cause autothreading to malfunction, thus I can't totally diagnose that part of the problem with the current cover. However, if I manually thread the tape through the path and onto the take-up reel, I can watch the dump process where it tries to lower the tape into the vacuum columns.

DUMP FAILURE FOR MANUALLY THREADED TAPE ON DRIVE A

I could see the dump process well with the acrylic cover in place. The take-up reel released tape forming a loop right in the middle of the lower vacuum column, exactly where it should stop. The supply reel released tape which fell all the way to the bottom of the upper vacuum column and caused the tape check.

WHERE I BELIEVE THE DRIVE IS MALFUNCTIONING

Based on the testing I did with the clear cover, the failure is with the servo loop that lowers the tape into the upper vacuum column. Specifically, it is not stopping the supply reel motion when the tape hits the middle of the column nor reversing direction as it should when the tape loop passes by the lower four photocells.

The failure could be:

• LEDs and/or photocell board failure causing logic board to miss the tape loop
• Logic board failure so that it doesn't properly respond to the tape loop in slowing or reversing the supply reel
• Servo loop failure so that commands to slow, stop and reverse the supply reel motor are not properly handled

I will use the logic analyzer signals to see what the logic board is being told about the upper tape loop. That will help me choose between the possible locations of the fault listed above.

Starting repairing Control Logic Board for drive B

CAREFUL EXAM UNDER MICROSCOPE

I subjected the board to a careful examination under the stereo microscope, looking closely at every component and wire for signs of damage. I found a broken capacitor that sets the time constant for a one-shot DM96L02 thus disabling this timing pulse.

I also saw one electrolytic capacitor that looked a bit dodgy to the eye and applied a resistance test to it. Fortunately it passed the sniff test so it doesn't need replacement.

REPLACEMENT OF BROKEN CAPACITOR

The schematic gave me the value for the capacitor and fortunately I didn't have one at hand, so off to Anchor Electronics and, nine cents later, I had what I needed. I desoldered the old one and installed the new one, putting the board back into apparent full working order.

TESTING OF LOGIC BOARD IN DRIVE A

It malfunctioned in a slightly different way, but still rotated the supply reel for a few seconds at power up. It also failed to load properly since it couldn't reverse the direction of the reel for the first step of the load sequence.

So much for the unrealistic hope that everything wrong with the board would be visible as damage and easily corrected by replacement of a part. Real debugging ahead, tracing signals around the board until I find the defects.

It would be easiest to debug if I had a card extender, but I don't. I considered designing one and sending it to fab, as long as I can find the female connector into which the card is inserted.No luck finding a 35 x 2 row .156" connector at Digikey, but I widened my search. I did find a 36x2 connector of the proper spacing on eBay and given its low price, bought it.

When the connector arrives next week I will decide whether to build an extension board using this socket. There are other ways, a bit more cumbersome, where I can put micrograbbers on specific component pins/leads and slide the card all the way into the card cage.

Building clear cover for vacuum columns to assist in debugging

HIDDEN TRANSPORT PATH AND VACUUM COLUMNS

The path that the tape takes past the head and into the two vacuum columns is hidden behind an aluminum cover plate, blocking a chance to observe what is working and what is failing during the autoloading. The maintenance manual identifies a service tool that was available - a clear plate to install.

Cover plate hiding tape path and vacuum columns

Since I don't have that plate and there is little chance I would ever find it, the only way I can peek inside is to manufacture my own. The plate has many holes to clear screws and tape heads, as well as holes that apparently help control the airflow to route the tape through the path. It will be a complex piece to design and build, but ultimately worthwhile.

Tape path around left perimeter and two vacuum columns

BUILDING A CLEAR PLEXIGLAS COVER

I took the plate off drive B so that I could carefully measure it out for entry into a CAD program of some sort. I suspect that the number of curves and drilled holes take this beyond the capabilities of TAP Plastics, thus it likely will require laser-cutting.

Cover plate to be replicated in clear acryllic

I will use Ponoko.com to do the cutting. I first have to build the design using Inkscape, an open source and free alternative to Adobe Illustrator. My door fits in a 23 7/8" by 11 1/2" rectangle but the closest common material size offered by Ponoko is P3 which is 31.1" x 15.1".

The shape is complex, even before all the holes and cutouts get added inside the remaining outline. I began by cutting down the outer shape, which took some time and ingenuity in the case of the arcs of unknown radius. After I traced the arc and continued it around a sheet of paper, I could determine the radius and distance from the perimeter to the far edge of the cover.

I then decided I would get better results if I were to take a picture of the cover, import it into Inkscape as a layer and then trace everything on the next higher layer. I had sized the picture so the image dimensions matched quite well, ensuring that my final design will correct. That gave me a good set of circles, paths and other shapes that fit well.

Laser cut file

I then uploaded it to Ponoko.com and selected clear acrylic of the appropriate size as the material. This gave me a set of costs, including premiums for faster production and for speedier shipping. They started at just over $21 not counting shipping, which was a minimum of Priority Mail. I upgraded to 3 day manufacturing which resulted in a total of $40. It should arrive late on the 18th of November.

Attempting manual load of tape on drive in Cabinet A of Telex 8020

MANUAL LOADING

The drive logic is set up for manual loading (or when a drive loses power with tape wound on the take-up reel) where it will dump the tape into the vacuum columns and then begin seeking the BOT marker.

RESULTS OF ATTEMPT

Threading the tape through the transport is annoying since the drive is really designed for autoloading, but I was able to get it through and wound around the take-up reel. In fact, as I wound the tape I saw the Load Point light flick on, which helps validate that the Beginning of Tape sensor and logic works properly.

However, when I hit the Load button, the top reel allowed its tape to buckle out of the entry slot in the tape transport and not load down into the upper vacuum column. Sigh. I will need to do more tape path and loading debugging. Sure wish I had the clear plastic alternate cover for the transport chamber.

DISCOVERED BAD CONTROL LOGIC PCB FOR DRIVE B

My recent tests with drive B were done with two PCBs I had swapped in from drive A - the control logic PCB and the reel pre-amplifier board. Since I was going to move back to drive A for the manual loading test I described above, I wanted to move those boards back where they belonged.

When I put the original two boards into drive B, the place they sat when I acquired the drives, at power-up the supply reel began rotating slowly clockwise. This occurred without having pushed the Load button at all.

Through process of elimination I determined that the Control Logic Board is the one that is malfunctioning. None of the LEDs light up on the board. I have the board pulled out and will have to do a very careful examination as the first step in diagnosing this problem.

Updating channel specification for 370 features

NEW REFERENCE DOCUMENT OBTAINED

I found a new manual that defines the 370 channel specifications. It is a replacement for the earlier document but has a similar name. It is GA22-6974-x IBM System/360 and System/370 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information.

CHANGES FROM 360

Additional Signals

One of the enhancements was to provide a two byte wide data path through the addition of a third cable which hosts a second set of Bus In and Bus Out signals. To differentiate use of this from the usual two cable single byte interface, IBM added some control tags in the Bus cable. These are Mark 0 Out, Mark 0 In, Mark 1 Out, Mark 1 In, Mark Out Parity and Mark In Parity. They are ignored by most control units but Mark 0 In is used for command retry.

IBM added Data Out and Data In tags to support a high speed feature. These are ignored by control units that don't use the facility. I will probably need to implement these just in case future uses of this channel will attach to very high speed devices.

IBM also added a Disconnect In tag that signals some I/O errors. It was a previously reserved signal on the cable thus it will only be generated by control units designed to work with 370 channels. Only some control units have this feature.

Additional Protocol Sequences

Disconnect In is used to assert that a control unit has an internal malfunction such as a processor error that won't allow it to use normal channel protocols to respond, thus the channel should abandon efforts to communicate with this control unit.

Mark 0 In is used to request Command Retry, where the control unit asks the channel to send a command another time because something stopped it from working properly the first time. The logic behind this is that the control unit expects that it may be able to successfully execute the command at a later time. This is either immediately or when the control unit signals it is no longer busy.

High Speed Transfer alternates the use of Service Out and Data Out tags (and correspondingly Service In and Data In) which allows operation at higher rates than the interlock specs dictated using only Service Out/In.

Beginning design of an FPGA based 370 channel, needed to drive my Telex tape drives

THE NEED

Once I have the tape drives able to load tapes and move them forward and backward, I will run out of tests I can accomplish solely with the tape subsystem. To be able to send commands to the drive over the channel, as well as cause it to write and read back data from the tapes, it needs a 370 Input-Output Channel such as would be on an IBM mainframe of the era.

This means I can't really verify whether the read/write circuits work properly without a channel. Simple movement doesn't prove it can handle commands such as forward space past next tape mark. Also, the status and sense bytes that need to be returned can't be viewed without the channel to request them.

THE APPROACH

I chose to implement a 370 channel in an FPGA because this will be useful for a number of future projects in addition to testing my tape drives now.  This will require me to control 16 outputs and receive 15 inputs. In addition I will output a periodic Clock out and steady low Meter Out, terminating and ignoring Meter IN.

These are designed for SLT logic levels (+3 for high, 0 for low) with specific thresholds, currents and protections. This will be addressed by use of converter PCBs that build drivers with an LVCMOS (3.3) input and receivers that produce an LVCMOS output, but are SLT at 92 ohm impedance on the cable end.

This FPGA channel must be fast enough to handle the 781,250 bytes per second coming from a tape drive, thus a data rate of more than 6.25MB/s. I have to define a connection and protocol from the fpga to some computer where I can generate the software channel programs, source data for writing and receive data and sense information.

In my initial implementation my link to the computer does not need to support 6.25MB/s as each channel program and its data can be preloaded at slower rates, then results fetched at slower rates, as long as the actual transfer over the bus and tag occur at the full rate.

RESEARCH MATERIALS

I will use several references in building the specifications for my FPGA channel. The goal is to have definitions of state machines and logic equations for all output signals based on the states. When that is ready, coding it in VHDL will instantiate the machines.

IBM publishes a document that locks down the specifications over the Bus and Tag cables. It is A22-6843-x, IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information. This will be the first source. I need to understand updates that may have occurred by the time of the 370 version of the channels, which may be a different manual title or otherwise documented by IBM.

Telex schematics show me how they implemented the channel interface for the tape drive controller, which I can cross reference to be sure I understand the IBM documents. Some of this is implemented in firmware in the control unit ROM, thus may require quite a bit of effort to extract for understanding. One has to understand the architecture of the controller engine then must examine each instruction to see what it does.

We (will) have access to the full schematics of the IBM 360/50 mainframe. We already have all the microcode. The channel microcode and schematics show how IBM implemented the channels in the 360 model 50 which is another cross reference to validate what I learn from the documents.

The material from the 360/50 will not include any enhancements made for 370 channels and upon which the tape drive may rely. Hopefully I can back-fit the enhancements to my understanding of 360 channels.

The 360/370 channels come in three flavors, although one of them is not appropriate for use with high speed devices such as the tape drives. These are Byte Multiplexors, Selectors and Block Multiplexors. IBM spells their multiplexer channels with an 'o' - Multiplexor.

Selector channels are for high speed devices and will be busy during the entire channel program. Thus, if the tape has a 10,000 byte record and transfers at 781,250 bytes per second, it will tie up the channel for 12.8 ms until the transfer is done. Worse is when the channel program is searching for a specific record header on disk where up to an entire rotation of time can be required; the channel stays busy for this. Selection is for the transfer of an entire block at a time.

Multiplexor channels are for low speed devices. They select for the transfer of a byte of data then disconnect. This allows multiple slow devices to be overlapping their data transfer, as they multiplex their bytes over the channel.

The Block Multiplexor channel allows for concurrent command chained operations for each device, thus more than one device may be searching for a disk sector but they remain disconnected until the condition is satisfied. Data transfer overlap depends on the speed of the devices, the speed of the channel and the overhead of the control unit requesting the reconnection.

Restoration of power supply and bring-up of integrated 3803 equivalent control unit for Telex 8020 tape system

PURPOSE OF CONTROL UNIT

These tape drives are intended for use on an IBM mainframe type system, which uses input-output channels connected via a pair of cables called bus and tag. The IBM equivalent tape system was the 3420. A set of 3420 drives had a separate cabinet, the 3803 control unit, into which the bus and tag cables were connected.

The 3803 then had cables hooked to the 3420 tape drives which implemented a simple protocol, with lines to command specific mechanical actions and wires to transport 9 bits of data in and out. All the error checking, formatting and decoding was done in the 3803 control unit.

Telex designed the 8020 tape drives as a compatible alternative to the IBM 3420 system. To offer space savings as an additional inducement to customers, on top of a substantially lower price, Telex designed their control unit to fit inside the first tape drive of a string.

The Telex tape drives implement their own simple protocol, over ribbon cables, to command mechanical actions and read/write 9 bits of data. The control unit speaks this Telex protocol on the ribbon cables and uses the IBM channel protocol on the bus and tag connectors. It performs all the error checking, formatting and decoding too.

REMOVAL OF CONTROL UNIT

I began to move the big, heavy box out of my drive cabinet A to begin the restoration effort. It is more than a foot high, the width of the cabinet and spans from front to back. Coming out of the box are ribbon cables that run to the bus and tag connectors as well as to the various tape drives that would be controlled by this system.

Telex directly soldered them to the bus and tag connectors, thus removal of these would have to come from inside the control unit enclosure. I opened the top to get the lay of the land but the cable routing is quite dense.

I discovered that the entire card tray can slide out and then pivot up to give access to the backplane pins, thus there is no need to remove the box from the drive to do my debugging and restoration. I replaced the anchoring hardware and moved on to the first step of restoration - good power.

RESTORATION OF POWER SUPPLY

I can get access to the power supply from inside the front door of the tape drive, hopefully enough to do any repairs it might need. I first removed the front cover plate, but behind it was a solid heatsink wall so that went back in place. Next I removed the top plate and looked down at the innards including three large electrolytic capacitors.

Control Unit power supply electrolytics

I unscrewed one lead on each of them in order to test the capacitor's condition. I also pulled the connector from the power supply to the backplane in advance of applying first power assuming the capacitors check out okay.

I used my capacitance meter first and confirmed they were all at about 72,000 uf, appropriate for filtering the three supplies. Next I hooked up my ESR meter and confirmed that the equivalent series resistance of these is under 0.06 ohms. At the current of 1A that would only drop .06V when the circuit was fully pulling from the capacitor, much less for handling ripple. These are all good.

Capacitance meter used to verify electorolytics

Meter to measure equivalent series resistance (ESR) of capacitors

The power supply produces three voltages - +15V, -15V and +5V - thus the three filter capacitors we see. The control unit is built with TTL logic and op amps, thus determining the voltages required. Other components such as discrete transistors are designed to work within these voltage levels.

Another early check I applied was to test the jack from the controller logic for dead shorts across the three power supply rails, since I have already found two small filter capacitors on logic boards with dead shorts while restoring other portions of the system. All power rails exhibited the behavior of charging up the filter capacitors, quickly getting to acceptable resistance levels. As an arbitrary example, a 20 ohm total load for the 5V rail would demand 1.25 A from the supply.

Next up I wired up a plug for the controller. It uses an ordinary household style plug given its much lower consumption, so I needed to wire up a socket for that sized plug that would in turn have wires poked into the 240V socket. A bit sketchy but okay for testing purposes.

240V socket for controller (see sketchy wires pushed in bottom socket)

I plugged it in, pushed the on switch and watched for signs of life (or magic smoke escaping). Time to test the three voltages while plug J3 is unhooked from the logic drawer. I saw +5.0, +15.0 and -15.0, exactly what should be generated.

The next and probably final step at this time is to hook up J3 to everything else and turn it back on.
Since I don't have a powered-on tape drive nor legitimate channel cables hooked up, this won't be happy but I can at least watch the status LEDs for boot-up of the processor and indications that the two ends are unconnected.

The signs of successful startup of the controller are LEDs producing a repeating moving dot display on the processor board and two LEDs that indicate the channel adapter initialized properly.  That is exactly what I saw, suggesting that all is good. The processor runs self-diagnostics during power-up and didn't find anything wrong.

LEDs lighting to show successful startup of controller

Debugging of Telex 8020 cabinet B drive

ATTEMPTING LOAD ON DRIVE B

After hooking up all the wiring and hoses, I powered up the drive with a tape on the supply reel and pushed the Load/Rewind button. The vacuum powered up but no reel movement occured. I watched the diverter valve solenoid to see it pull in to select load mode versus its default run mode.

No solenoid movement. I put the meter across it and no voltage was delivered to the coil. I then began probing the connections to the driver board. It is provided with +12V and -12V plus a signal control line. The line is pulled up by the driver board and grounded by an open collector inverter on the control logic board.

Testing the lines quickly showed me that the +12V rail is not active. I know that the power supply will shut that off if there is a short circuit, such as I had with the bad capacitor on the dump card when restoring the power supply.

I decided to yank cards out of the machine until I figured out which one is shorting the +12V bus, without harm to the rest of the machine. I switched off the +45V and -45V so they don't provide power to the motors, pulled the power amplifier and pre-amp cards, then monitored +12V.

The voltage was zero again, so I yanked all the cards except for the control logic to ensure I had valid +12V as a starting point. I installed the read, write and AGC boards next had the voltage disappeared. A bit of a binary search led me to the write card which had a dead short across the +12V rail.

It was another of those black polarized capacitors, a 15uf 20V molded unit, similar to the one that failed shorted on the dump card. At this point I distrust all of these, but only the one is bad at this time. If I were to keep the drives in service, I would go through and swap out all of these for new tantalum axial capacitors. As it is, I am ordered a batch of 10 as replacements since these are so troublesome.

Shorted 15uf filter capacitor on the Write board

Now the diverter valve works, the supply reel turns to try to find the end of the tape on the PEOT vacuum sensor, but I seem to be missing the blowing air that forced the tape end up in the air. This may be because of the broken plastic part where the forklift crunched the tape drive.

Indeed, it is because of the damage. Further, the allen bolt that holds one end of the plastic down is bent, thus unable to get the part to seat firmly enough for the rubber gasket to keep the blown air channeled to the proper place.

Damaged plastic part with air hole visible

Channel for air to blow the end of the tape off the reel

I should make a rubber or plastic right angle diverter that sits in the air outlet hole and blows it towards the edge of the tape to make it lift up. It may be possible to buy a new allen bolt and flatten the area to make a proper seal but I am doubtful, so auto cartridge load is ruled out for drive B.

Damaged surface where o-ring and plastic part need to seal

THREADED TAPE AND ATTEMPTED LOAD

I realized that the control logic will see tape in the path and a vacuum on the take-up reel hub, understand that tape is already wound on the drive, and simply attempt to dump the tape into the vacuum columns. I hand threaded the tape and hit Load/Rewind, but the tape in one of the columns bottomed out causing a Load Check. One of the servos or one of the LED sensors is malfunctioning - it appears to be the upper column.