More debugging of write functionality of Virtual 2315 Cartridge Facility

RESOLUTION OF PREVIOUS ISSUES APPLIED

During testing of writing from the IBM 1130 to the Virtual 2315 Cartridge Facility (V2315CF) I had identified two areas of concern. First, the power supply that converted the 12V produced by the 1130 computer system down to 5V for delivery to the main unit of the V2315CF had periodic voltage glitches about every 30 microseconds. Second, the clock signal generated by the V2315CF that is delivered to the 1130 circuits so they can transmit the data stream for a write had several issues.

The power supply problem was due to economy mode operation because the DC to DC converter in the power supply was loafing along with the demands of the V2315CF relative to its 10A capacity. This caused it to turn off the switching oscillator and turn it back on every 30 us for a brief burst. That created a ringing of the supply with over 1 volt swing during each burst. 

The fix was to add about 2A of power dissipation using carbon power resistors so that the supply did not need to enter economy mode, as well as adding a couple of filter capacitors where the 5V enters the main unit of the V2315CF. The oscilloscope confirmed that the wild swings every 30 us had been managed. We now have less than a millivolt disturbance on the incoming 5V to the V2315CF main unit.

5V rail swing with scope set to 200mv per major division

The signal issues included a logic high level that never reached 2V, a major undershoot from ringing, and a slow rise time of the signal. The source of the signal is an open collector gate, which is what gives the dramatic falling edge. The slow rise time and low voltage at the 1130's input pin is due to the high value pullup resistor at the V2315CF and the capacitance involved in the long complex path between the V2315CF unit and the 1130's logic gates. 

The fix was to install a 169 ohm pullup resistor to 5V and a 249 ohm pulldown resistor to ground on the terminator board on the V2315CF. That gives a much stronger pull-up and ensures that the high voltage at the 1130 logic gate is much closer to 3V. It ensures a faster rise time for the signal. Lastly, it should provide a better impedance match to the signal path which hopefully will quench most of the ringing at the falling edge. Again, the oscilloscope on pin B03 of card slot K6 of compartment C1 in the 1130 logic gate A showed a better behaved signal. It is still low, having to do with the effects of all the resistances in the circuit, but the skipped shifts no longer occured. 

Some of the ringing is due to poor scope lead grounding

BETTER TEST RESULTS WITH WRITE IN VIRTUAL MODE ACHIEVED

This time I did achieve a capture of the data I wrote to the virtual 2315 cartridge with no shifted bits. I set up a known pattern in a memory buffer in the 1130 and issued an XIO instruction to write to a given sector of the disk (cylinder 0, head 0 and sector 1).  After clearing out the memory buffer, I issued an XIO to read in the same sector, confirming that the contents matched what I had written - up to a point!. An offline view of the mini 2315 cartridge using the Showsector.exe program I provided confirmed the content of the sector as well. 

The 1130 wrote 159 words out of the 321 correctly - zero errors encountered. However, it did not write anything other than zeroes for the remainder of the sector. This behavior is consistent - always gets the first 159 words captured correctly and then seems to give up on the write.

DEBUGGING REASON FOR EARLY TERMINATION OF THE WRITE

Writing is supposed to commence at the end of the sector marker pulse that defines the beginning of the sector we are writing into. The 1130 should wait 250 microseconds, controlled by a timer (single shot) gate, then begin emitting the sync word pattern. From the end of the sync word detection, it should write out the 321 words requested, shifting each word out as 16 data bits plus 4 error checking bits (total 20). 

These are transmitted in the bit cells that take 1.45 microseconds each, thus each word consumes 29 microseconds and the entire sector would require 9.39 milliseconds. Before the data begins shifting out, the duration of the initial sector marker pulse (160 microseconds), the 250 microsecond timer, and then the 29 microseconds for the sync word are added on top of that total. This gives us a 9.748 milliseconds out of a 10 ms sector. 

When I looked at the logic analyzer output, I did notice that the sync does not finish until about 650 microseconds not 278.7 microseconds as I would have expected. This exceeds the time budget we have! It should result in a slightly truncated sector, but we are seeing about half a sector written before it stops. 

Thus I have identified a few issues to resolve. First, I think the bit cell duration is too long and is causing the data to spill over out of the sector. Second, it appears that the timer that controls when the sync word appears is out of adjustment, starting the data portion of the sector some 375 microseconds later than it should. Third, the write is ending about where a sector marker pulse is arriving since they come once every 5 ms or twice per sector. 

Bit Cell Timing

The original design I developed, consuming 1.45 microseconds, is the equivalent of only a 690 KHz clock rate while the internal disk drive is nominally operating at 720KHz. That is the equivalent of almost 13 words that can't be fit in the sector because of the wastered time. 

The specification of the internal drive is a bit cell duration of 1.39 microseconds at 720KHz. I can get close with a simple change to my design, providing a bit cell of 1.40 microseconds or 715KHz clock rate. I think this is close enough and will make that happen. 

The FPGA operates at a 25 nanosecond clock time, which gives me the choice of the bit cell duration being 1.375 or 1.4 microseconds. There is a way to generate a different clock frequency that yields exactly 1.39 uS but then using signals generated require synchronization because we now have two clock domains that have to interact. For the time being, I will stick with the 1.4 uS as that is less than 1% off the spec.

Duration of the Preamble Before the Sync Word

The disk rotates at 1500 RPM and has eight equally spaced notches that produce sector marker pulses. Since a rotation takes 40 milliseconds so a sector marker pulse occurs once per 5 ms. The sector marker pulse drops the -Sector Marker signal for 160 microseconds then returns it to logic high. 

One of the sector marker notches has a second notch next to it, which produces a special Index Marker pulse once per rotation. This disk controller logic increments a counter on each sector marker pulse, but resets the count to zero when it sees the index marker. That ensures that the counter is always reporting the correct sector. 

The index marker pulse also sets a divider circuit which produces a signal called -Four Sector Pulses  which skips every other sector marker. Thus, we see four of the eight sector markers on that signal line, one for each of the four sectors that we write to. 

When we write to the disk, the command specifies a sector number so that the disk controller can turn on the -Write Gate signal to start the write when we match the sector number and the sector marker from the -Four Sector Pulses signal arrives. When the sector marker pulse ends after 160 microseconds which kicks off the writing on the -Write Clock and Data line. 

A single shot timer is started when the -Sector Marker signal returns to logic high. It is set to emit an output for 250 microseconds. During this time, bit cells are being written with the data value of 0. This is roughly 179 bit cells of zero. When the timer shuts off, the disk controller logic begins writing out words, the first of which is the special sync word. 

This means that the last preamble cell ends 410 uS after the sector marker pulse began. After another 27.8 uS, the sync word has completed and the controller begins writing 321 data words each taking 27.8 uS. In an ideal world, that means the entire sector ends after 9. 361.6 uS leaving 638.4 uS of spare space. 

However, our sync word as measured on the 1130 system ended at 690 uS into the sector instead of the expected 437.8 uS point. The timer must be seriously out of adjustment. Luckily it is an adjustable single shot and I will tune it 250 microseconds. I will also verify that the sector marker pulses are approximately 160 microseconds. If they are longer, it could also be a contributor to the late end of the sync word. 

Explaining the Point Where the Write Aborted

When I look at the data that was written into RAM when the write occurred, it ends at word 159 instead of continuing to 321. This is close enough to the halfway point in the sector that it is possible that somehow the sector marker pulse that is NOT part of -Four Sector Pulses is causing the write to abort. I don't see anything in my logic that could connect that, but if the issue is in the IBM 1130 disk controller logic then it might have aborted the write by deasserting the -Write Gate signal. 

Unless I can figure out some mechanism that could cause the V2315CF to stop the write, I need to do some diagnostics with the logic analyzer to figure out why the short write is happening. I will watch the signals like -Write Gate, -Four Sector Pulses, and -Sector Marker. Hopefully I can get a quick clue that will explain why I am seeing the exact failure that is occurring.