Friday, August 5, 2022

Feeling good about generating a read head stream of pulses but not done yet

›
IMPROVED FAKE MEMORY MODULE TO SEQUENCE VARIOUS DATA WORDS I made changes to the fake memory module such that it would produce a known strea...
Thursday, August 4, 2022

Substituted fake memory module for the real memory interface - speeding debugging

›
INSTANTIATING A MODULE WITH THE SAME INPUT OUTPUT BUT MINIMAL LOGIC I took the interface design of the memory controller module and used tha...
2 comments:

Quick update on simulating DDR3 memory interface

›
SIMULATION MODELING PROVIDED ONLY FOR VERILOG The models that will accurately simulate the DDR3 memory interface I generated and permit me t...

More learning curve - memory interface generator, DDR3 memory and FIFO startup requirements

›
SIMULATION SHOWED FIFO BEGIN FULL When I begin my debugging of the RAM access mechanisms that would be driven by the disk modeling to fetch ...
Wednesday, August 3, 2022

Bitstream generation and disk modelling verified through simulation

›
THE MECHANICS OF A SECTOR ON THE DISK DRIVE As you remember from prior posts, each bit written on the disk is an approximately 1.4 microseco...
Tuesday, August 2, 2022

Finishing the drive modeling and simulating as I go

›
ARM MOVEMENT MODELING FULLY TESTED I put the logic through its paces with simulation to ensure that I will properly capture the position of ...

Validation of drive modeling in FPGA by simulation is well underway

›
TWO OF DRIVE MODELING READY TO DEBUG In order to inject the proper bits into the read circuitry of the physical drive or to snag written bit...