Probing further into the OneDark signal mystery

WORKING ON ONEDARK UNTIL IT BEHAVED

I removed the ceramic disk capacitor and replace it with a new one, just in case that was causing the voltage divider behavior. I also saw that OneDark is connected to other cards via the backplane and the issue could have stemmed from a bad chip elsewhere.

I did some substitution of cards from my working M600 reader, as well as pulling various combinations out to see when the spurious voltage level arose. At some point during all this moving and checking, the voltage went solidly near 5V. From that point forward, the OneDark signal was behaving correctly.

I am unhappy that I don't have a clean culprit as the problem can come back, but for now I have to move on to debug what I can see is defective. Looking at the trace of a card going through the reader, I can see the OneDark popping on which immediately triggers the next couple of steps. 

The Good Pick Reset signal goes high for four clock phases, which begins the operation of the PRCLK which counts the time from when the leading edge is detected by OneDark until the point where the column 0 exists. PRCLK is decrementing a counter with a preset amount based on the known card speed of the particular model. 

Meanwhile, a rotating wheel with teeth is triggering pulses from a magnetic sensor. As soon as a pulse arrives, the OSCLK should be cycling causing the offset counter to count up until the PRCLK decremented counter goes to zero. That time is when the card column center is under the photocells, thus that offset count will be remembered. Later, when each new column arrives, a third counter begins incrementing by signal OSUCLK until it matches the value in the offset counter. The match triggers the CSDS signal that we are at a column.

Alas, I don't see OSCLK nor OSUCLK operating. I do see that the sync logic controlling those counters is reset by the ST0B signal. The signal is inverted, meaning it should be high most of the time and them blip low when gated to pass a phase B cycle. When I check the level, however, it is low all the time. This is wrong.

ONE ISSUE AT A TIME - STOB SIGNAL NOT APPEARING

The ST0B signal is emitted by a NAND gate which has phase B clocks going high on one input and a signal from the sync logic when the saved offset counter matches the counted offset for this column. Only when both are high should the gate emit a low output. One input is cycling with phase B, the other is always low when not reading cards, yet the output of the gate is low. I will replace this chip and see where we get to next.

EXTENDER CARD IS NEARING THE WORKSHOP

I received notification that the Extender Card that was donated to me by a fellow restorer working at the Datamuseum in Denmark has reached the US Postal Service in Chicago which means it won't be too much longer before it is delivered to me, connectors installed, and put into good use debugging the card reader.