Some incompatibilities, appears I can resolve them to use 32M flash in place of 4M flash chip

SUBSTITUTION POSSIBILITY FOR FLASH CHIP ON IOB6120

The IOB6120 was designed to use a Sharp flash memory chip, the LH28F400BHVE-BL85, but that chip is so obsolete that there are not even entries for it with suppliers like Digikey or Mouser. I did find a very limited supply of a newer Sharp flash memory, which is larger but uses the same TSOP 48 pin layout and has almost full pin compatibility. Thus, if I can resolve any conflicts and verify that it should operate properly, I can install this 32Mb flash chip in place of the 4Mb chip in the design.

BYTE MODE USED ON DESIGN CHIP, DOESN'T EXIST ON SUBSTITUTE

The chip used in the design is a 4Mb chip that either addresses 256K 16 bit words or 512K bytes. The substitute does not offer a byte mode, it always returns 16 bit words and thus the 32Mb chip addresses 2M locations versus 256. This uses three additional address bits for the new chip, and on the old chip it needed an extra bit to select the upper or lower byte of a 16 bit word.

ADDRESS BIT OVERLOAD OF Q15 PIN ON DESIGN CHIP

The old chip, for which the IOB6120 is designed, allows selection of the upper or lower byte of a word by using data bit 15 as an input, called the A(-1) address bit. This works in byte mode because the data bits 8 to 15 are floating, not driven, when in byte mode. D15 can be used as an input in that mode.

The substitute chip, however, drives all 16 data bits in output mode, which would conflict with the driven A(-1) signal hooked to D15. This is the biggest conflict in the use of this chip in place of the design part.

POTENTIAL RESOLUTION INVOLVES MINOR REWORK ON BOARD

If I cut the trace delivering the A(-1) address bit to D15, then the output will be driven but have no destination. That is fine since we have plenty of extra words in this larger substitute chip and can afford to only use the bottom 8 bits of each of the 2M words, which is still more than the 512K bytes the design chip addresses.

I would then route the A(-1) bit over to one of the three unused high address pins on the new chip with a jumper wire. Assuming these pins are not grounded through to the inner plane, the only question is where I pick up the A(-1) signal for the jumper over to the address pin such as A20 I would use for my modification.

MAJOR QUESTION ON CUI MODE DIALOG WITH FLASH CHIP AND DATA BIT 15

This device is designed to operate in SRAM compatibility mode for reading - simply supply an address, strobe the appropriate select and output enable control pins, and you are able to read to the chosen address. If the design only uses this mode, then all will be well if I resolve the A(-1) bit address issue as discussed above. 

On the other hand, this chip also needs the Command User Interface (CUI) mode to do writes. CUI sends commands and data to the controller onboard the chip. The 4Mb chip will handle CUI on the low 8 data bit lines when the chip is put in Byte mode, as it was in the IOB6120 design. The 32Mb chip handles CUI over the full 16 bit data width and therefore probably will not work properly with D15 bit floating and commands and data sent only on the low eight bits. 

ALTERNATIVE FOUND AT A HIGHER PRICE 

I did discover a newer Sharp flash chip that supports the byte mode and thus would be fully pin compatible, simply with higher capacity that the chip in the design. It is the LH28F160BJHE-BTLTH also TSOP 44 format and its higher capacity makes use of pins that are N/C on the design chip.  Looking for quotes at a reasonable price but I can pay $20 for four of them on eBay and hope they are not counterfeit.