Beginning project that is possibly too large to be feasible - full netlist and locations of the IBM 1130

CONSIDERING THE NETLIST AND CONNECTIONS TO DEAL WITH BROKEN TRACES

Since I already have found two backplane traces that were broken, which are on different backplanes and physical locations, the odds are high that other such failures exist. Correcting them is a simple matter of adding some wire wrap connections. 

The challenge is in finding them. A signal may only occur in special cases, for example a multiply where an overflow occurs or some special combination of timings. I am unlikely to be able to run a sufficiently comprehensive set of tests to find every one of them; some may produce subtle malfunctions that are hard to spot. 

A method guaranteed to succeed is continuity testing each connection. If I take the simplifying assumption that these failures are all from edge connectors inward, rather than potential failed traces within a backplane from card slot to card slot, then this list would give me the information I would need to beep out each netlist signal. 

The time to execute the continuity test is pretty substantial. There could be a max of 20 edge connectors on a board but 12 is a more reasonable average. A connector has 24 pins; we will assume a usage of 20 per connector. This means that each compartment has 240 pins whose destinations need to be beeped. 

If I complete the beeping and verification of a pin in 30 seconds, it will take 120 minutes per compartment. Six exist on this machine so 12 hours of beeping once I have the netlist. 

COLLECTING IMPORTANT INFORMATION

This will involve two passes through all 226 pages of ALD. The first will generate all the outputs (right side of the page) plus the off compartment connections and the pins of cards within the page connected to that output signal. The second will record where each input signal runs to pins on the page, where an input was an output previously recorded from some other page. 

I chose to collect the following information as fields so that I can sort this different ways to get full use out of it:

• Gate - A, B, C, D or E
• Compartment - A1, B1 or C1
• Slot - A1 to N8
• Pin - B02-B13, D02-B13, G02-G13, J02-J13, plus bottom/top pins
• Netlist name - ALD page name plus signal location, e.g. BB101AA4
• Signal name - logical signal name, e.g. -IO Bit 3

POSSIBLY TOO BIG AN EFFORT TO FINISH

With 226 pages producing perhaps 20 output locations per page, we are looking at over 5,000 line entries in the spreadsheet. This will take quite a bit of time to collect and will be tedious work. A rough guess is four pages per hour, four hours per day max time I can put onto this, thus two weeks to complete. 

I may discover that some internal traces are broken, while debugging various issues on the machine. If so, there are a huge number of possible connections to test, with up to 20 signals per SLT slot and up to 66 card slots in a compartment (backplane). Not every slot is populated and not every pin is assigned. 

As an estimate, if we assume 40 cards per compartment and 16 signals per card, we have to beep connections between 640 pins. I won't need to do any exhaustive search of all combinations of the 1320 total pins, since my project could, in a third pass, produce just the pin to pin connections I need to test.