Debugging my way through the capture of writes to the disk drive and proper storage onto the virtual cartridge image

LOGIC ABLE TO ORIENT ITSELF TO THE FIRST BIT OF THE FIRST WORD ON A WRITE

The pattern for a new sector is to have zeroes written for 250 us after the sector mark pulse, one sync word to establish the timing of clock versus data pulses and the start of each word,  then  up to 321 words of 20 bits each. The timing of the clock versus data pulses is handled for me by the drive emitting the two phases of the 720 KHz write oscillator and sending the data bits only during phase B.

However, it is important to spot the sync word as that tells us how to split a long stream of 6, 440 data bits into words. My logic begins watching during the early part of the sector when only clock pulses are written, in other words when the bit cells are all data value 0. As soon as I see a 1 bit written from the CPU, I assume it is the sync word. 

Each word from the IBM 1130 is 16 bits long, written back to front on the disk, with four check bits appended. Thus the sync word appears to be a string of fifteen 0 bits, a 1 bit, then the appropriate four check bit pattern of 1110. When I see the 1 bit, I test that the next three bits are 1 and the last one is 0. If this is true then we have correctly synced up and know that the immediate next bit is word 1, bit 15.

If this is not true, I turn on a signal that is generated by the drive to signal some kind of writing error in the circuity that makes it unsafe to write on the disk. This signal will make the drive go "Not Ready" and signal the error status to the CPU. It can only be reset by spinning the drive down to zero and turning it back on. 

I tested this with a variety of error conditions as well as the proper bit pattern for the sync word and am satisfied that this works properly.

Test catching and validating the sync word

In the simulation run above you can see the two clock phases A and B, the pulses on the Write Data Bit line from the CPU that would be detected and the state machines for disk rotational modeling at the top and the write capture machine below the two clocks. In between the clocks and data bits you can see the bit counter that tracks the number of 1 bits in a word in order to validate the check bit pattern.

CONTINUING TOMORROW WITH THE WORD EXTRACTION

Up next is the testing of the logic that accepts 16 bits, 15 down to 0, turning them into a parallel word with the bits 0 to 15 from left to right, then verifies the four check bits of the 20 bit recorded word. Any error in the check bits will be cause for me to turn on the same write unsafe error condition to make the drive Not Ready, as this blocks any further words from being written onto the virtual cartridge. 

I have already set up the testbench with four words of data following the sync word, all properly formatted with the appropriate check bit patterns. It will allow me to verify the operation of the logic to extract words and ask the memory controller to write them to RAM.