VOLTAGE LEVEL CONVERSION CIRCUITS BREADBOARDED
The FPGA input output pins are set to LVCMOS 3.3V logic levels, but the Atmel Mega 2560 processor operates with TTL 5V signal levels, thus I have to insert a level shifting circuit in the SPI link lines MOSI, MISO, SCK and Slave Select, as well as with the SPI transaction flag line.
When I build the final production version of the Virtual 2315 Cartridge box I will have manufactured a printed circuit board to hold the level shifters, which also are needed for the thirteen lines between the IBM 1130 disk drive and my FPGA board.
WIRED UP THE TWO BOARDS AND SET TWO STARTUP TRANSACTIONS
I tied the grounds of the two boards together and then snaked the signal lines through the level shifter breadboard. The Arduino code was modified to loop sending two initial commands over the SPI link, turning the RAM access over to drive mode and then switching it back to SPI mode. Success will be immediately visible on color LED 0 which will shift to blue when the board is in drive mode.
OBSERVATIONS DURING THE FAILED COMMUNICATIONS
The clock of the SPI secondary channel never oscillated, nor did I see any action on the MOSI line. This tells me that the channel was not initialized properly or there is some other defect. I verified this on the TTL (+5V) side as well, it is not a level shifter failure.
LIKELY ISSUE IS SETUP OF THE SECONDARY SPI CHANNEL ON THE ARDUINO
I need to walk through all the documentation from Atmel on setting up the USART for SPI Master mode as something is definitely not right with my Arduino sketch.
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