Tweaking toolchain to compile code for HPS system

FIRST STEP IS BUILDING THE HEADER FILE FOR THE HPS CODE

The toolchain provides commands that read the files which generated my FPGA side for the SoC - pulling out the hardware components and the assigned addresses in memory to reach them from the program running in the HPS side. 

It establishes various constants that are used to create the virtual addresses when one has to control the bridges or access other peripherals that are attached to the FPGA side. The resulting header file is included in my user code that will run under Linux. 

FIGHTING PATH ISSUES RUNNING THE HEADER FILE CREATION SCRIPT

The toolchain is built from nested batch files, scripts and programs, but somehow it doesn't install itself in a way that will actually work immediately under Windows 11. First up, the batch file create_hps_qsys_header.sh fails because the system can't find sopc-create-header-files. When I explicitly point at the folder holding this, that fails internally calling sopcinfo2swinfo.exe and I suspect there would be further failures if I did a spot fix for that. 

ROOT ISSUE - SHIMS AND RUBE GOLDBERG ADAPTIONS

At heart all the toolchains appear to be Linux executables. Graphical interfaces are shimmed above them even for the Linux environment but then in Windows we introduce the cygwin environment to run Linux under windows, yet another shim. 

This obscures what is actually taking place and introduces many failure points with the shimming. In the Xilinx toolchain I would find that when things went awry it would leave files or not properly update files which are essentially undocumented and hidden by all the shims. If this were a simple command line environment than all the files would be overt and much easier to dig into when chasing bizarre behavior.

The toolchains for the Intel/Altera SoC environment are split into two parts - one for compiling code to run on the HPS side and one to build logic for the FPGA side. These two, Quartus Prime and Soc EDA, are both distributed separately and sometimes included in the same download. 

I suspect one of my issues right now is that I downloaded Quartus Prime 17.0 which installs under the FPGA Lite path, while Soc EDA 17.0 installed under a plain FPGA path. The materials on the web sites and documents are frankly terrible at specifying what order or what products to download, thus it is unclear whether I should have just installed SoC EDA and accepted Quartus as part of it, or if I did the sequence right with Quartus first, then Soc EDA. 

In any case, more completely wasted time chasing issues that have zero to do with my design or my own code. Zero.