Minor issue with Quartus build of my SoC design - damned toolchains again

CHECKING IO PIN ASSIGNMENTS AND FOUND MISMATCH

As part of my desk checking, I was cross checking the external connector pins I had assigned to the logical signals within my Field Programmable Gate Array (FPGA) and the Hard Processor System (HPS) sides of the System on a Chip installed on this board. The manual for the board lists the SoC chip pins associated with each connector pin, but I quickly discovered that these did not match. 

There were very serious mismatches, as for instance the main clock input to the SoC was on the wrong pin. As a result, the board would have sat there mutely doing nothing. After double checking that the SoC chip was the Cyclone V 5SEBA6U2317 which was configured in Quartus toolchain, I began searching the web for others experiencing mismatched assignments.

Voila - I quickly found that the assignment of these is either done manually or by a tool provided by Terasic - SystemBuilder. It updates the xxxx.qsf file in Quartus to make various assignments for IO pins. This step was not done on my project, for a very good reason. 

THESE ASSIGNMENTS SET BY TERASIC SYSTEMBUILDER TOOL - IN WINDOWS

The tool provided by Terasic is a windows executable. It does not have a Linux counterpart. It also produces a Verilog top level file, rather than VHDL as I would have preferred, but I long ago rolled with the punches to use the top level as it was.

Thus I moved all my VHDL files and the top level Verilog file over to the Linux instance, created the new project and then set up my SoC and other logic statements. This did not carry over the contents produced by SystemBuilder in the xxx.qsf file, thus I didn't have the proper assignments. 

FOLDING IN SYSTEM BUILDER STATEMENTS INTO MY FILES ON LINUX

I used SystemBuilder to create a dummy project with its high level file and xxxx.qsf file. That file was transported via USB drive over to my Ubuntu image and I merged this with my project. The proof of the pudding will be proper pin assignments for all the important signals. 

REBUILD OF THE DESIGN

Alas now the toolchain can't see my SoC design from Platform Designer (QSYS), thus it can't do the compile process properly. It appears that I must go all the way back to step 1, using the output file from SystemBuilder on my Windows machine as the input to a fresh project. I can then import all my other VHDL modules and tediously set up the SoC in Platform Designer. 

This is the kind of issue that arises from a fragile toolchain that is a patchwork of layers and add-ons. The way forward is very clear and success is assured, so I will be starting over now.