Bench testing the replacement 5806223 card for correct functionality - found error

SET UP THE CARD ON THE BENCH AND POWERED IT

The card has a number of input signals:

• -DC Reset which is held low when the machine first starts
• -B Bits 0, 1, 2, 3, 4 and 5 which indicate requested plotter movements
• +XIO Write
• +Area 5
• +T6
• +XIO Sense Device
• +XIO Sense Device with Reset 15
• -24V from the plotter

It produces six outputs where +12V will drop to 0V for short periods to command the 1627 plotter. It also generates a request for an interrupt on level 3 and outputs status bits 0, 14 and 15 when an XIO Sense Device is executed. 

I wired all the external connections with wire wrap (30 ga) wire, except for the +12V and ground lines which use 26 ga wire. These will be soldered onto the appropriate pads of the donor SLT card to connect the signal to the desired SLT connector pins. 

RESULTS OF TESTING

So much was working properly, but I stumbled on a problem where anytime the B register bits go on, it will trigger movement of the 1627, not just during an XIO Write to the device. This was the result of my misreading the datasheet and I didn't catch the error when I breadboarded everything.

THE ISSUE IN TRIGGERING THE 74LS122 SINGLE SHOT

I have 122 chips that should fire off a short pulse when the CPU is executing an XIO Write, for Area 5 (the plotter), during time step T6 and the B register bit is on for that requested movement. If the B register bit is not on, nothing should happen. Importantly, nothing should happen if we are not executin the write command. 

As I looked at the function table with its four inputs A1, A2, B1 and B2, I simply misinterpreted it. I had hooked up the B register bit to input B1 and input A1 would be high when the write command was executing. 

The third line in the table shows that when B1 is low, the outputs is off. I took this to mean that B1 was a gating input, when low nothing would happen. I should have looked carefully at the dagger symbol † because it is only true about retriggering, once some set of inputs fired off a pulse. 

Once a pulse is fired, if neither of the A inputs is high and neither of the B inputs is low, the chip will repeatedly fire off pulses until the inputs change. If an A is high and/or a B is low, this is a single shot, not repeating. 

If you look further down the table to the fifth line, you will see that even when A1 is low (not a write command), a rising edge on B1 will fire off a pulse. Thus any time the B register bit goes high, its leading edge causes this chip to fire off a pulse. Not at all what I intended.

MISSED DURING BREADBOARD TESTING BUT SPOTTED WHILE BENCH TESTING

Somehow the way that I set up the inputs to test the circuit while it was breadboarded didn't toggle the B register bits. I either set it up with the bit on, or the bit off, and activated the write command signals. It must have misbehaved but I wasn't watching carefully. I only verified that the pulse reliably set the flipflop for the 1627 movement comment and emitted the signal to that device for the desired time period based on another set of 122 chips. 

While bench testing, as I slide the switch up to turn on the B register bit, the pulse fired and turned on the flipflop, in spite of the A1 signal indicating that we were NOT in a write command. I set up a 122 chip back on the breadboard and exercised it to confirm to myself that the function is not what I had assumed. 

ALTERNATIVE WIRING WILL ACCOMPLISH THE SAME OBJECTIVE

Looking at the function table, I realized I could use the CLR input as well as some changes to the A and B inputs to accomplish my goal. Specifically, B1 is set high, as were B2 and A2 already, then when the CLR is released (rising edge) if A1 is low, the pulse will be emitted. 

The CLR pin is wired to the write command condition - it is low except when an XIO Write to Area 5 occurs during T6 when it goes high for the length of T6 (450 ns). If A1 is low at this time, I get a pulse. The input signal is actually -B Bit n so that it is low when the bit is on. The input is wired directly to A1 of the 122 chip. 

The prior implementation required me to invert all the -B Bit n signals since I believed I needed a logic high to fire off the pulse. I can therefore eliminate entirely the 74LS04 chip U4 from the design when corrected. 

BELIEVE I CAN BODGE THIS BOARD TO VERIFY OPERATION BEFORE I ORDER NEW PCBS

If I cut the traces to the CLR, B1 and A1 pins of the six 122 chips responsible for requesting the six 1627 movements, bodge wires could bring the intended signals to the chip. When I look at the PCB design, however, the connections for the CLR pin (pin 5) cause difficulties. A1 and B1 are routed out from the chip so that I could cut away the traces. CLR is routed underneath the chip and in a number of cases, is part of an integral path bring +5V to other pins on the chip so it can't simply be severed. 

What is possible is to lift pin 5 on those chips, so that the CLR pin does not contact the pad below that is at +5V. Tacking a wire to the lifted pin will give me the means of accomplishing my bodge. I will put an insulator (something like nail polish) on the pad to avoid accidental connection of the +5 to the CLR pin. 

WILL RESPIN THE PCB DESIGN, WAITING TO SUBMIT UNTIL REMAINING TESTS DONE

In addition to the removal of U4 and the wiring changes for the six 122 chips I detailed above, I found that one of the external signal pads was labeled incorrectly. It should read -DC Reset but is +S reset instead.