Testing 1130 MRAM board - defect in design identified

LOCATION ZERO IS SET TO VALUE OF ZERO DURING A SYSTEM RESET

I saw two categories of problems while testing the memory board, now that I have the system power more reliable (but not still fully fixed). First, when more than a few bits are set to 1 values, the data does not seem to be reliably read back into the Storage Buffer Register (SBR). Second, many times when I hold down the Reset button (or at power on reset), the contents of location zero is set to all zero bits. 

I dug into the timing of various signals when the machine comes out of reset and to find vulnerabilities that will result in a spurious write being commanded of the MRAM chip. The logic for controlling the lines +Storage Use, +Storage Select, +Storage Write and +Storage Read produce unexpected values as a reset condition is release, which triggers my board to perform a write operation. 

+Storage Use will be on at any time except for a storage cycle when the 1130 does not want to access memory, thus it is on immediately as reset is released. +Storage Write is on immediately after reset is released and also during the entire time that reset is active. 

It is even possible that this flaw in the design could cause problems at other times while the system is running, but in any case it must be corrected. 

REFINING THE USE OF CONTROL SIGNALS BY MY BOARD

In systems using the faster 2.2 microsecond core memory type, the signal +Storage Select will emit a short pulse when the processor steps into states T0, X0, T4 or X4, which will trigger a storage cycle as long as +Storage Use is also high. In normal processor execution, each storage cycle takes eight T clock steps, T0 through T7. The first half of the storage cycle, T0 to T3, is when +Storage Read is high. The last half is when +Storage Write is high. Thus the IBM core memory logic is triggered by the pulse as long as +Storage Use is high, but does a read or a write based on whether +Storage Read or +Storage Write is high. 

In the 3.6 microsecond memory type, such as the machine into which my board will be installed, +Storage Select is driven by the high address bits to select which core memory compartment is active. In the machine I am restoring, there is only one gate so this is effectively always on. In fact, the core memory logic in that compartment does not even look at a +Storage Select signal since memory in gate B compartment C1 is ONLY used with 4K or 8K configurations of 3.6 uS core. 

MAJOR PIVOT IN DESIGN OF THE BOARD

I decided to ditch the timer modules and instead depend on a small FPGA to handle the timing. I designed around the Digilent CMOD S7, a Spartan 7 board. It has enough input-output pins to make the operation of the board fully flexible. I did have to add a 5V power supply regulator to feed the CMOD. 

Now, the pulse to write a 1 into the Storage Buffer Register (SBR) for each of the 16 data and 2 parity bits is an individual line for each bit. Since the existing board works okay for a small number of 1 bits but fails with larger groups like 6 or more, having individual control would allow me to stagger the pulses across the bits so that any funny analog issues that arise from the simultaneous activation are avoided. 

I also control the individual control signals for the MRAM chip - Write, Data Out and Enable - so that I can refine the timing of the activation if needed. Even the buffer chips which block the incoming SBR bits from the memory during reads but pass them through on writes is controlled by the FPGA. 

This definitely requires a change and a new PCB to be fabricated. I also have to write the Verilog for the FPGA, but that is dead simple for this case. While the board is being manufactured, I can write and test the code. Then, when testing, I can adjust timing of signals to refine the behavior of the board.