Great discovery solving my IO pin shortage

REASSIGNABLE EXTERNAL CONNECTIONS VIA PERIPHERAL MUX TABLE

The Qsys utility of the Quartus toolchain is where the System on a Chip (SoC) is configured particularly the Hard Processor System (HPS) and its links to the Field Programmable Gate Array (FPGA) side. I discovered a great feature as part of that tool.

One aspect of configuring the HPS within that tool is setting up the peripheral pins you will use, such as the ethernet or Serial Peripheral Interface (SPI) functions. At the bottom of that screen is the peripheral mux table. The table lists every external connector pin of the chip as rows of the table, and within the column it shows alternative functions that could be routed to the pin. 

At first I thought of this as a warning, since very function can't be configured simultaneously. One of the columns of that table is labeled Loaner IO. After a bit of reading, I realized that you could select any external connector pin that wasn't in use by a selected function of your design and route it to the Loaner IO. 

Loaner IO is a bus that is connected across to the FPGA side. For each of the 67 rows of pins, this bus allows the FPGA side to set the pin as input or output and to access the signal from the FPGA. This offers the ability to give the FPGA side even more pins than it has directly connected. The reverse of what I needed but it was a hint that what I needed was indeed possible. 

GPIO ACCESS IN LINUX

The corresponding column in the peripheral mux table to the Loaner IO is the GPIO signals. These are signals that can be accessed from within Linux as long as you selected the external connector pin to be routed to its GPIO peer. They appear to the FPGA as tri-state connections, thus I can ignore that end and access it purely from my Linux application. 

SPI MASTER HAS TWO VASSAL SELECTS AVAILABLE, LCD AND TOUCH

The included SPI Master 0 on the SoC offers two select pins, thus it can directly select between two xxx SPI devices using the Linux driver. One will control the LCD panel and the other controls the touch screen that sits over the panel. These are standard assignments which don't require any special actions to enable. Note that using the second select pin takes over one of the UART external connections, thus we can't have UART and the dual select SPI master at the same time. 

TOOK OVER UART AND CANBUS PINS VIA LOANER IO FOR REMAINING SIGNALS

The second UART connector pin I routed to a GPIO that I will write from my application, to control the LCD Command/Data pin of the LCD module. I picked one of the external pins normally tied to the Canbus link for my HeadsLoaded signal which I can read from the application to verify that the physical drive has not spun down. 

BOTTOM LINE ADVANTAGES

I no longer need to solder onto the USER KEY button on the HPS side, nor to use bridge signaling to pass signals across sides. The mux table plus GPIO gives me the ability to get the extra signals to the HPS side.