Well, almost correct solution

LOOKING FOR THE ACTUAL CONNECTOR PINS FOR CANBUS ETC

My great idea to simply reassign to connectors like the Canbus interface depends on their having been an external pin. There is not. Some of these functions may be routed to a connector, as is the case when either SPI or I2C is instantiated and automatically routed to the 2x7 LTC connector, but others have no physical instantiation. 

I still need to find external pins for HPS signals related to the LCD interface module as well as receiving signal HeadsLoaded to detect when the drive turns off. Not deterred, I looked deeper into all the capabilities they offer in the System on a Chip (SoC) IC. 

ANOTHER WAY TO EXPORT SIGNALS FROM HPS TO FPGA

The only logical function for which I needed to export signals was the Serial Peripheral Interface (SPI) master, which is controlled by its driver under Linux. The other signals are something that I will read or write via the General Purpose Input Output (GPIO) method I wrote of previously.

I therefore set up GPIO signals for the following:

• select LCD panel
• select touch screen
• stream is data or command
• reset LCD
• HeadsLoaded signal

I found that the Qsys system exported those as conduits, signals I can access from the FPGA and therefore hook them to various external pins (confusingly also called GPIO). I have the five HPS side GPIO signals exported along with the SPI master clock, MOSI and MISO lines. These will all be connected to selected pins on the other type of GPIO, a physical connector on the board. 

GETTING THE INTEGRATED TOP LEVEL MODULE IN SHAPE TO BEGIN TESTING

Since the top level module produced by this toolchain is in Verilog, but I am most familiar with VHDL, I have to create instantiation templates for every one of my VHDL modules, which is a somewhat tedious process of capturing the entity declaration from VHDL and then modifying it to fit the Verilog format as an instantiation. 

Next up was the routing of signals between the various modules. Each external signal from the IBM 1130 requires synchronization to avoid metastable conditions, passing it through a chain of flipflops clocked by the FPGA to get the edges aligned with our clock rather than the autonomous 1130 clock.