Continued testing of 1130 MRAM board - more probes added to zoom in on problem area causing retriggering

ADDED EXTRA ENERGY PATHS TO VCC AND GROUND ON THE NAND CHIP

I added wires to the VCC and ground pins of the 74HC00 chip to lessen resistance to current flow that might be causing voltage drops that 'bounce' the ground or 3.3V power flows to the chip. I previously did this for the SN74LVC1G123 timer chips that are retriggering, but the worst behavior I am seeing is coming from the NAND gate that drives the timer. 

RETRIGGERING EXISTED BEFORE MY TRIGGERING MODIFICATIONS

Originally the design had the +Storage Read signal directly connected to the timer chip trigger (~CLR pin) but I realized that this was a design defect, so I began to AND this signal with the +Storage Use signal before triggering the timer chip. The problem was that +Storage Read will always occur even when the storage cycle should not use memory, instead gating data from peripheral devices for example. 

The timer will ALWAYS produce pulses to set the B register bits for any bit of the MRAM chip on my board that has a 1 value. The MRAM chip will always output the value in memory of the word addressed by the current SAR register address bits, thus if any are a 1 then they will flip on the B register during cycles when it shouldn't, like the peripheral I/O case I mentioned. 

The modification I made to solve the incorrect B register setting issue mentioned above was to use one of the four NAND gates on the 74HC00 chip, reroute signals like +Storage Use and +Storage Read, switch the timer chip to trigger on a falling edge by changing the ~A, B and ~CLR input values, and connecting the newly used gate to the different trigger pin of the timer. 

Due to existing traces to the pads of the 74HC00 and timer chip, I had to cut traces, lift up some chip leads off the pad of the board, and use bodge wires. This is messy and caused several rounds of resoldering of the chips that might have introduced solder joint issues. 

I see the worst of the signal anomaly on the output of the newly used NAND gate, but I was having the retriggering problems before all this so the root cause predates the modification. My modification may be more susceptible but isn't sufficient to explain it. 

SOLDER JOINTS HAVE BEEN A PROBLEM WITH THIS BOARD

Putting the very small surface mount parts on the board is a challenge, since a soldering iron tip is larger that the space between chip leads. It is very easy to have blobs form across multiple leads causing shorts, which I had to wick up with solder braid. The resulting cleaned off joint might appear to be a good connection but not actually have metal fused between the bottom of the lead and the pad on the board. 

In hindsight I should have used solder paste and a hot air gun to solder the tiniest chips to the board, achieving a good connection without the messiness and errors that crop up with traditional soldering.