Continued testing of 1130 MRAM board - results of probed points and added power wires

TRACES OF KEY SIGNALS AFTER CHANGES TO BOARD

No change with added power lines to the chips. A dead end I believe.

FOUND SHORTED OUTPUT LEAD ON WRITE TIMER CHIP

The reason my write timer chain wasn't producing pulses was a consequence of my having tacked a wire onto the lead to observe it. Somehow the trace came a bit loose and the trace plus lead moved over to touch the adjacent pin, which on this chip is ground. 

I removed the chip with my hot air station then soldered it back down with solder paste and the heat gun. The write time now fires when +Storage Write has a rising edge.

RETRIGGERING HAPPENING ON BOTH READ AND WRITE TIMER CHAINS

The same issue arises on the write timer chain - as the first timer output pulse ends, thus triggering the second timer, there is noise on the +Storage Write trigger signal and the first timer repeats. The write timers are on the other side of the PCB from the read timers, yet have the same behavior. 

WATCHING SOURCE GATE IN 1130 ALONG WITH RETRIGGERING AT PCB

The source signal from the originating gate in the 1130, compartment B A1 card J2, has the same glitching as the +Storage Write signal onboard my PCB. These are the same as what happens on the +Storage Read signal and its timer chain. 

Purple is source gate, yellow is input to my timer chip

This did get me thinking. Every problem like this is an analog circuitry problem, masked by the digital abstraction of timer chips or NAND gates. The timer chip does not come with a schematic of the internal circuitry thus I can't model this exactly. What might be happening inside the timer chip, the cable and the 1130 gate that could do this?

SUSPICION OF BACKFEED OF VOLTAGE FROM TIMER CHIP THROUGH ITS INPUT

I am wondering if the SN74LVC1G123 timer chip is somehow backfeeding the +Storage Write (and +Storage Read) lines as it finishes its timed pulse. The SLT logic in the IBM 1130 uses +3V for logic high and that is what we see on the +Storage Write line when it is active. The chips on my board, however, are operating at 3.3V not 3V.

What if the shutoff of the pulse somehow delivers 3.3V back to the input pin, perhaps through a protective diode, which then rings based on the impedance of the cabling and the details of the source gate in the 1130? When my board is disconnected, the signal from the 1130 looks great. When my board is connected, there is ringing even back at the source. 

EXAMINING DETAILS OF SOURCE AND DESTINATION GATES IN 1130

I will look at the analog circuitry in the gate producing the +Storage Write (or +Storage Read) signal and at the gate in the IBM core memory compartment that normally would have received the signal. That will give me component values that I can plug into models in LTSpice where I can see if I can explain the ring or resonance based on capacitance, inductance and the resistances in those gates and the cabling between them. 

Sadly I don't have the schematic for the TI timer chip to model its input properly, but I can make some assumptions and see whether I can explain the waveforms I am seeing.