User interface test verification part 27

THE EVIDENCE IS PILING UP THAT THE DEVICE TREE FOR U-BOOT IS BAD

The U-boot archives that get downloaded in order to generate a new version of U-boot to reflect the settings you want in your System on a Chip (SOC) such as the Cyclone V in my Terasic DE10-Nano board, generate a stripped down device tree that is used by the preloader and by U-boot to know how to execute on the ARM processors, how to get to and initialize the DRAM memory and how to communicate over the serial port. 

Somebody, usually the maker of the board, provides the base device tree source for the board and the default configuration settings to allow the make process to build a working preloader and U-boot. Over time as the tools that manipulate the device trees evolve in newer versions of U-boot, one would hope that somebody was responsible for verifying that they still work properly. That may not be correct.

I have two archives I am working with. One is the official U-boot code stream and another is a version of U-boot that was modified by Altera, the original designer of the Cyclone V SOC chip. Neither of these create an image that boots up on my board, not even to issuing the first messages on the console. 

I grabbed the two device tree blobs that were created for the preloader, converted them back to device tree source using the device tree compiler dtc, and looked closely at them. Neither of them seems complete enough to allow the preloader to work. 

DTS FILE FROM OFFICIAL U-BOOT ARCHIVE AFTER MAKE OF PRELOADER

One issues only two commands to build a preloader and U-boot. First, run the vendor provided default configuration file. Second, run a make all. The file socfpga_de10_nano_defconfig is the file that is run to set up for a U-boot that should run on the Terasic board. After the make all is run, it has created a folder SPL that holds the preloader. In that, a number of transformations are run on the files from the archive in order to produce u-boot-spl.dtb a device tree blob for the preloader. 

Here is what was produced when I ran this through dtc to recreate a device tree source. 

/dts-v1/;

/memreserve/ 0x0000000000000000 0x0000000000001000;

/ {

#address-cells = <0x1>;

#size-cells = <0x1>;

model = "Terasic DE10-Nano";

compatible = "altr,socfpga-cyclone5", "altr,socfpga";

aliases {

serial0 = "/soc/serial0@ffc02000";

};

soc {

#address-cells = <0x1>;

#size-cells = <0x1>;

compatible = "simple-bus";

device_type = "soc";

ranges;

clkmgr@ffd04000 {

compatible = "altr,clk-mgr";

reg = <0xffd04000 0x1000>;

};

l2-cache@fffef000 {

compatible = "arm,pl310-cache";

reg = <0xfffef000 0x1000>;

cache-unified;

cache-level = <0x2>;

arm,tag-latency = <0x1 0x1 0x1>;

arm,data-latency = <0x2 0x1 0x1>;

prefetch-data = <0x1>;

prefetch-instr = <0x1>;

arm,shared-override;

arm,double-linefill = <0x1>;

arm,double-linefill-incr = <0x0>;

arm,double-linefill-wrap = <0x1>;

arm,prefetch-drop = <0x0>;

arm,prefetch-offset = <0x7>;

phandle = <0x1>;

};

dwmmc0@ff704000 {

compatible = "altr,socfpga-dw-mshc";

reg = <0xff704000 0x1000>;

fifo-depth = <0x400>;

#address-cells = <0x1>;

#size-cells = <0x0>;

resets = <0x6 0x36>;

status = "okay";

broken-cd;

bus-width = <0x4>;

cap-mmc-highspeed;

cap-sd-highspeed;

};

rstmgr@ffd05000 {

#reset-cells = <0x1>;

compatible = "altr,rst-mgr";

reg = <0xffd05000 0x1000>;

altr,modrst-offset = <0x10>;

phandle = <0x6>;

};

sdr@ffc20000 {

compatible = "altr,sdr-ctl", "syscon";

reg = <0xffc20000 0x6000>;

resets = <0x6 0x3d>;

phandle = <0x2f>;

};

sysmgr@ffd08000 {

compatible = "altr,sys-mgr", "syscon";

reg = <0xffd08000 0x4000>;

cpu1-start-addr = <0xffd080c4>;

phandle = <0x25>;

};

serial0@ffc02000 {

compatible = "snps,dw-apb-uart";

reg = <0xffc02000 0x1000>;

reg-shift = <0x2>;

reg-io-width = <0x4>;

dmas = <0x32 0x1c 0x32 0x1d>;

dma-names = "tx", "rx";

resets = <0x6 0x30>;

clock-frequency = <0x5f5e100>;

};

};

memory {

device_type = "memory";

reg = <0x0 0x40000000>;

};

chosen {

bootargs = "console=ttyS0,115200";

stdout-path = "serial0:115200n8";

};

};

DTS FILE FROM ALTERA U-BOOT ARCHIVE AFTER MAKE OF PRELOADER

The resulting device tree source from the Altera version of U-boot is:

/dts-v1/;

/memreserve/ 0x0000000000000000 0x0000000000001000;

/ {

#address-cells = <0x1>;

#size-cells = <0x1>;

model = "Terasic DE10-Nano";

compatible = "altr,socfpga-cyclone5", "altr,socfpga";

chosen {

bootargs = "console=ttyS0,115200";

};

soc {

#address-cells = <0x1>;

#size-cells = <0x1>;

compatible = "simple-bus";

device_type = "soc";

ranges;

u-boot,dm-pre-reloc;

dwmmc0@ff704000 {

compatible = "altr,socfpga-dw-mshc";

reg = <0xff704000 0x1000>;

interrupts = <0x0 0x8b 0x4>;

fifo-depth = <0x400>;

#address-cells = <0x1>;

#size-cells = <0x0>;

num-slots = <0x1>;

broken-cd;

bus-width = <0x4>;

cap-mmc-highspeed;

cap-sd-highspeed;

drvsel = <0x3>;

smplsel = <0x0>;

status = "okay";

u-boot,dm-pre-reloc;

};

};

};

This file does not even have an entry for memory, which fully explains why nothing takes place when I boot this preloader. It can't find DRAM in order to initialize it, copy in its code and continue execution. It refers to ttyS0 for the console but does not contain any entries defining that. At least the top file has an alias for serial0 to an entry for the serial port where the messages should be issued. 

This appear to me as fragments of what would be needed to make the preloader actually function. I need to investigate a few things in order to figure this out and then find a way to correct it. It would have been helpful to have documentation that tells you what the parameters must be in the device tree for the preloader, but that doesn't exist. 

FIGURING OUT WHAT IS MISSING AND HOW TO FIX IT COMES NEXT

Somehow I need to see a working device tree source for this board. It may be that the transformation tools in U-boot have evolved and no longer process it correctly but that it did work at some time in the past with an earlier version. Too, I might be able to locate and dump the device tree blob from within the working preloader I have from the Terasic distributions, allowing me to see what should be in there. 

The harder method would be to read through and understand the hundreds and hundreds of source code files in the U-boot archive and then study all the hardware configuration steps and register configurations that would be needed to run the preloader. Again, no documentation that spells this out, so it requires digging through many thousands of pages of Cyclone V and other documentation. Possible but very high work effort. 

User interface test verification part 26

ATTEMPTED TO RUN OFF FLATTENED IMAGE SUPPORT BUT MAKE PROCESS FAILS

My boot files are the traditional compressed Linux kernel and a device tree blob (DTB), not the flattened tree that combines them into a different structure. I thought that the boot might be failing because the preloader (SPL) was looking for the flattened image file and wanted to eliminate that code as a stab in the dark.

I changed the default configuration file to specify CONFIG_FIT=n which would turn off all the code for flattened images. When I then tried to make U-boot and the SPL, it failed trying to build all the DTBs for the various types of boards that use the Altera/Intel SOCFPGA chips. The first it tried, the Agilex N6100, failed with an error that it couldn't find binman in the DTB it was processing. Binman is used for trusted boot, which we are not using with the Terasic DE-10 Nano board, but is required for the Agilex one.

I don't know why the make process insists on building every DTB for every SOCFPGA chip when we are in fact doing a build for one specific board, but it does. It has a very very convoluted process of scripts, makefiles and other tools that result in the attempt to build all the DTBs. There is no method I can find to block it and the SOCFPGA section of U-boot apparently cannot successfully complete a Make if FIT is deselected. 

This represents the issue with the System on a Chip products and toolchains. You can skim along doing almost exactly the same as the reference/example projects, but once you step off that cliff edge you plummet to where you need to understand virtually everything about complex subjects just to move forward. I am forced to gain considerable expertise in U-boot, for example, both the actual code and the make process, just to get a working loader. Getting features of the SoC chip to work required diving very deep into the chip architecture, the toolchain and other topics. Essentially this is a pool with one step at 6" depth and the next step is 10,000 feet down requiring deep sea diving gear. Nothing in between. 

DIGGING INTO OTHER DETAILS IN CONFIGURATION FILES

There are hundreds of configuration settings, any one of which might be the cause of the failure to boot up SPL. I will first look into every setting that explicitly mentions SPL, dig into the hundreds of source code files and work out what it does. As one example, the start address for SPL is set to 0x08000000 in the configuration file. Not sure why that is the number and more importantly what number it should be. Will report on what my research uncovers and whether I finally (or ever, it seems like) find the smoking gun. 

Did some cleanup on the System Source 1130 system

RAN OVER TO THE SHOP TO IMPROVE SERVICEABILITY OF THE 1130

I had added a simple capability to the System Source 1130 system, just as I had designed it for mine and for The National Museum of Computing in the UK. It has a bank of relays wired to the console entry switches and several of the console pushbuttons. This allows the user to rapidly load any content into core memory without the time consuming effort of manually flipping switches and pushing buttons.

In order to load a word into memory at some location, one first sets up the load address by flipping the 16 console entry switches to the desired address. The Mode rotary switch is set to Load and the Load IAR button is pushed. This sets the Storage Address Register to the intended address. 

The user then sets the 16 console entry switches to the first data word to be entered, then pushes the Start button to load it into storage. The memory address is automatically incremented to the next sequential address, so that one can load subsequent data words by 'only' switching sixteen console entry switches and then pushing Start, for each one. 

Loading a very long program into memory is tedious and error prone using the physical switches and buttons. This modification installs an Arduino that drives relay boards to electronically set the console entry switches and to electronically push Load IAR or Start. The Arduino is connected via USB to a serial terminal, usually a laptop, where an ASCII file can be transmitted line by line. The file format uses characters like @ to designate setting the memory address otherwise the characters are the hex value to set in the console entry switches. 

Thus a very long set of words to put in memory is typed into a file as sets of four hex digits with optional prefix characters. That file is opened by the serial terminal program which looks for the prompt character coming from the Arduino before sending each line to be loaded into the 1130. 

The implementation required adding sixteen wires to the console entry switches, which are on the inside of the front panel of the 1053 console typewriter. The normal cable from that panel runs down into the 1130 logic gates but has some spare length to allow the panel to be moved from its fixed spot. This is because the panel is attached to the front of the console typewriter itself, so then whenever the typewriter must be removed for service, cumbersome disassembly is needed.

The typewriter is lifted off its normal location but is limited by the length of the console entry switch cable. The typewriter is turned on its side and screws are removed to detach the front panel with the switches. This allows the typewriter to mover over a bit further, but the typewriter is cabled into the 1130 with three SMS cards attached deep in the bowels. Two are the signals for the typewriter and one is the power for the device. These must be detached after unsrewing and swinging things around underneath, then snaked up to finally be able to move the typewriter to some remote workbench for service. 

When I added the Arduino based loader, I added my own wires to the back of the console entry switch panel. These were wired directly to relay boards screwed down between the keyboard and the typewriter front panel, under the tabletop. Thus, the front panel was further restricted, not just by the standard cable down to the logic gates but also by my new wires which were shorter. This made the cumbersome juggling even harder.

I therefore inserted a set of connectors so that my wires come out of the panel to a connector, then the wires from the relay boards run to the other connector. This allows separation of the wires so that the only anchor on movement of the front panel is the length of the standard IBM cable down to the logic gates. 

Quick feasibility investigation for emulating all devices on an 1130 for machines without the Storage Access Channel feature

THE PERIPHERALS CHALLENGE FACING MOST 1130 OWNERS

Most of the surviving 1130 systems, either in museums or private collector hands, do not have sufficient working peripherals to demonstrate the system adequately. Many did not have the input-output devices saved or they are very difficult to restore to operation. 

In order to show the machine in typical operation, we would want to have the internal disk drive, a card reader and a line printer operational. The demonstrator puts a boot card in the reader, loads DMS2 monitor from the disk cartridge and that prints a startup page on the printer. At this point, decks of cards can be read into the monitor and any output from the programs will print. 

While one can switch to the console to type in card images to fire up previously stored programs on disk and those programs might only write to the console typewriter, it is not feasible with DMS2 as it is written to get to that point without a reader and a line printer.

One can image a demonstration environment where the user types virtual cards into files on a support PC, has them read through a virtual card reader and any printed output from the 1130 is captured by a virtual line printer as another file. Systems that have a working internal disk drive but nothing else would be usefully demonstrated in this case.

Even more so, full emulation would allow a machine that did not have a working disk drive or other peripherals to boot up and run jobs, using virtual peripherals and files on the support PC. My own IBM 1130 is a mixed situation. I have a working 1132 line printer and working internal disk drive, thus with some work manually entering the boot card image to memory I can fire up DMS2 to the point of the start page printing. 

My 1442 card reader is not currently working, so that I can't do much more. I believe I could hack the DMS2 image to have it request card input from the console keyboard, allowing me to fire up previously loaded programs as long as they didn't need the card reader. 

I designed, built and installed an FPGA based box that connects to the IBM 1130 and implements virtual peripherals, such as additional 2310 cartridge disk drives, 1442 or 2501 card readers, 1132 or 1403 line printers and the 1053 console typewriter/keyboard. It attaches via a feature on the IBM 1130 that presents a large connector on the 1130 for a cable that would be hooked to other devices including the 1133 Multiplexor box that supports devices like the 1403 printer and 2310 disk drive. 

MY PREVIOUSLY BUILT EMULATOR DEPENDED UPON THE SAC FEATURE

IBM provided a set of signals on the Storage Access Channel feature that allows an external box, including their own 1133, to become device controllers for additional peripherals. It has the ability to send data in and out of the 1130, intercept the XIO instruction that controls peripherals, trigger interrupts and drive cycle stealing to access memory on behalf of the peripheral.

IBM attached devices through SAC such as the 1403 printer, 2310 disk drive, 2250 graphics workstation, 2420 tape drives, and others. Larger installations used the SAC to make use of these peripherals; my first experience with an 1130 at Florida Institute of Technology had a 1403 and two 2310 drives attached through an 1133. 

An 1130 itself can have device controllers for the 1132 printer, 1442 card reader, 2501 card reader, 1627 plotter, internal disk drive, 1053 console typewriter/keyboard, 1054/1055/1134 paper tape devices, the 12xx optical mark reader and the SCA communications adapter, but each is installed only if that peripheral were ordered with that 1130 machine. 

The SAC signals allow peripherals that make use of interrupt levels 2 through 5, but not levels 0 and 1. Those are used by the 1132 printer, the 1442 card reader/punch and the SCA, thus one cannot emulate these devices using the SAC connector. I therefore expanded the SAC with a second small cable that added signals for those two interrupt levels plus a signal to trigger a sequencer I also built to 'push' the three buttons needed for a boot - IMM STOP, RESET, and PROG LOAD. 

I am willing to share the design so that any owner of an 1130 that has the SAC feature can build my box and emulate any device on the 1130. One has to disable the internal controller for devices if emulating a device whose controller logic is installed in the 1130. In my case, to emulate 1442, 1132 or 1053, for example, I had to disable their logic in my machine to that did not try to respond to the XIO for the emulated devices. I did this manually. 

FINDING SIGNAL AVAILABILITY ON NON-SAC MACHINES

The SAC feature not only provides the connector, it implements line drivers to send the signals the relatively long distances over a cable and adds some logic that is not in the standard 1130 to handle some special cases needed by the 1133 and 2250 boxes. Thus I had believed it was not practical to emulate on non-SAC machines because of all the additional logic that was added.

It came to me, however, that I could capture signals with local PCBs I attached inside the covers of the 1130 and thus not need all of IBM's line drivers. The question was whether all the signalsspo needed for SAC were available on backplane pins of a machine that did not have SAC installed. I began to investigate.

I quickly found spots to pick up or inject almost all the signals. Injected a signal with IBM's SLT logic technology is easy - you find a line that is active when low and then just add a modern open collector logic gate to pull it to ground when you want it active. 

The nature of SLT circuitry is that this is perfectly fine to add and has no impact on the gates that are 'driving' the line high, since in reality the receiving gate has a weak pullup and the drivers only pull to ground or are inactive. 

There was a signal that was manufactured by a combinatorial logic circuit in the SAC version of the 1130 but not in the standard machine. This turned out to be a 5 way OR of signals which were available on the backplane pins, so I only needed to grab those five to produce the missing signal. 

A few inputs to the 1130 on the SAC commanded actions to stall the cycle steal clock, present data earlier in the cycle steal protocol than normal, to gate incoming data onto the CPU B bus, and to keep the CPU meter running while a mechanical peripheral was still physically active. None of these were needed to control when incoming data was put on B, as I could control that in my box through timing of asserting the incoming data lines. My emulated peripherals would not need to stall the cycle steal clock nor to enter data early, so those lines were moot. Finally, I don't care about running the CPU meter as I am not collecting hourly fees from renters of the 1130. Thus I didn't need any of these signals. 

On my system, I manually switched when disabling the internal device controller logic whenever I was emulating a peripheral that was configured into my machine. However, as I worked on the non-SAC version I realized that I could add a few more signal lines so that my box could disable the controller logic for any emulated device electronically. 

DETERMINATION - IT IS FEASIBLE TO MAKE SUCH AN EMULATOR

I carefully checked the locations against multiple sets of ALDs I had collected from various machines and am confident that this will work. It would require a small PCB located near four compartments on the two swing out logic gates of the 1130 - A gate compartment C1 plus on B gate all three compartments A1, B1 and C1. These small board would have wire-wrap connections from the compartment backplane and a connector taking the signals to the FPGA board mounted elsewhere inside the 1130. 

Essentially I would modify the FPGA logic I used in my SAC based emulator, which wouldn't be a huge job. The PC based application that communicates with the FPGA is attached via USB thus the 1130 would simply have a USB connector into which the laptop gets plugged to control the emulator. 

PROJECT MUST WAIT FOR CURRENT RESTORATION TO FINISH

I have an IBM 1130 I am restoring for the System Source Museum and it is already delayed while I finish the Virtual 2315 Cartridge Facility I developed. This has been bogged down in toolchain issues for too long already. I won't take on any additional project until I have the machine fully operational and ready for pickup by that museum. 

This will be very handy for owners of 1130 systems so that I will probably start on it after finishing the current 1130 restoration. 

User interface test verification part 25

DIGGING INTO POSSIBILITY THAT THIS IS A DEVICE TREE ISSUE

Before I begin hacking the code to the preloader (SPL) to give me clues about what is going wrong, I focused on the idea that the most likely cause is a failure to copy itself to RAM and load u-boot code. Most comments I found through extensive google searches pin this on errors in the device tree blob, so that was my focus for a couple of days.

The process of  building the device tree blob is not simple. There is a submitted file provided with the distribution of U-boot that presumably the maker of the board or a code contributor has provided. This is massaged in various ways to produce two device tree blobs, one for U-boot and a stripped down small one for SPL due to size limitations in the initial storage used for preloader execution. 

The initial source for the board is merged with various other source files to build up a device tree source. This is because a specific board has unique features but also shares a lot with every board built using the same SoC chip, in my case Cyclone 5, and in common with every Altera/Intel based SoC board regardless of the chip type. 

The C preprocessor will merge all those common elements with the board specific details to form the first source file. The device tree compiler dtc is then run to convert the source format dts file to a binary blob format dtb. This watches for a number of warnings as it processes the source file. 

All further processing is done on the binary format files thus harder to observe without converting the dtb back to dts format temporarily for inspections. 

The dtb file is combined with the compiled U-boot code in the next few commands. We then copy the dtb file to the directory where we will build the preloader (spl) and skinny it up.  A few passes through a tool called fdtgrep do the trick. The first pass drops everything that is not tagged with special markers u-boot,dm-pre-reloc and u-boot,dm-spl but also some special sections like chosen that are used to direct serial console messages. The second pass does more exclusion of specific properties within entries to further reduce the size of the resulting dtb file. 

The files are moved various places, the dtb files appended to binary files and then the specific bootable images are created using the mkimage tool.  Eventually we end up with four copies of the preloader (including its small dtb) then the U-boot binary with its larger dtb, forming the data to be copied into a special partition on the SD card from which the Cyclone 5 chip will boot. 

Something is going wrong in this process, perhaps, resulting in a dtb that doesn't give the preloader the data it needs to at initial DRAM, copy code and emit the first output to the serial console. We don't yet know if this is a missing or incorrect element in the dtb, a dtb that is so large it exceeds the limited SRAM space on the Cyclone 5 chip into which the preloader must fit, or something entirely different. 

Below is the extract of the make process that builds the device tree blob from the initial source and then uses it to create the SPL and U-boot images:

  mkdir -p arch/arm/dts/ ;

  

     (cat arch/arm/dts/socfpga_cyclone5_de10_nano.dts; ) > arch/arm/dts/.socfpga_cyclone5_de10_nano.dtb.pre.tmp;

     

     cc -E -Wp,-MD,arch/arm/dts/.socfpga_cyclone5_de10_nano.dtb.d.pre.tmp -nostdinc -Iinclude     -I./arch/arm/include -include/

      ./include/linux/kconfig.h -I./arch/arm/dts -I./arch/arm/dts/include -I./include -D__ASSEMBLY__\

       -undef -D__DTS__ -x assembler-with-cpp -o arch/arm/dts/.socfpga_cyclone5_de10_nano.dtb.dts.tmp arch/arm/dts/.socfpga_cyclone5_de10_nano.dtb.pre.tmp ;

       

      ./scripts/dtc/dtc -O dtb 

      -o arch/arm/dts/socfpga_cyclone5_de10_nano.dtb 

      -b 0 

      -i arch/arm/dts/ 

      -Wno-unit_address_vs_reg 

      -Wno-unit_address_format\

       -Wno-avoid_unnecessary_addr_size 

       -Wno-alias_paths 

       -Wno-graph_child_address 

       -Wno-graph_port 

       -Wno-unique_unit_address 

       -Wno-simple_bus_reg\

        -Wno-pci_device_reg 

        -Wno-pci_bridge 

        -Wno-pci_device_bus_num  

        -a 0x8 

        -Wno-unit_address_vs_reg 

        -Wno-unit_address_format 

        -Wno-avoid_unnecessary_addr_size\

         -Wno-alias_paths 

         -Wno-graph_child_address 

         -Wno-graph_port 

         -Wno-unique_unit_address 

         -Wno-simple_bus_reg 

         -Wno-pci_device_reg\

          -Wno-pci_bridge 

          -Wno-pci_device_bus_num  

          -d arch/arm/dts/.socfpga_cyclone5_de10_nano.dtb.d.dtc.tmp 

          arch/arm/dts/.socfpga_cyclone5_de10_nano.dtb.dts.tmp 

          ||

           (echo "Check /home/carl/Documents/quartus/Virtual2315Cartridge/software/u-boot-socfpga/arch/arm/dts/.socfpga_cyclone5_de10_nano.dtb.pre.tmp for errors" && false) ;

            sed "s:arch/arm/dts/.socfpga_cyclone5_de10_nano.dtb.pre.tmp:arch/arm/dts/socfpga_cyclone5_de10_nano.dts:"\

            arch/arm/dts/.socfpga_cyclone5_de10_nano.dtb.d.pre.tmp 

            arch/arm/dts/.socfpga_cyclone5_de10_nano.dtb.d.dtc.tmp 

            > arch/arm/dts/.socfpga_cyclone5_de10_nano.dtb.d

            

  cat arch/arm/dts/socfpga_cyclone5_de10_nano.dtb > dts/dt.dtb

  

  cat u-boot-nodtb.bin dts/dt.dtb > u-boot-dtb.bin

  

  cp u-boot-dtb.bin u-boot.bin

  

mkdir -p spl/dts/

          ./tools/fdtgrep -b u-boot,dm-pre-reloc -b u-boot,dm-spl -RT dts/dt.dtb -n /chosen -n /config -O dtb 

              |

          ./tools/fdtgrep -r -O dtb - -o spl/dts/dt-spl.dtb -P u-boot,dm-pre-reloc -P u-boot,dm-spl -P u-boot,dm-tpl -P u-boot,dm-vpl/

             -P pinctrl-0 -P pinctrl-names -P clocks -P clock-names -P interrupt-parent -P interrupts

             

  cp spl/dts/dt-spl.dtb spl/u-boot-spl.dtb

  

  cat spl/u-boot-spl-nodtb.bin spl/u-boot-spl-pad.bin spl/u-boot-spl.dtb > spl/u-boot-spl-dtb.bin

  

  cp spl/u-boot-spl-dtb.bin spl/u-boot-spl.bin

  

  arm-none-eabi-objdump -t spl/u-boot-spl > spl/u-boot-spl.sym

  

  ./tools/mkimage -T socfpgaimage -d spl/u-boot-spl.bin spl/u-boot-spl.sfp >/dev/null  && cat /dev/null

  

  ./tools/mkimage -A arm -T firmware -C none -O u-boot -a 0x01000040 -e 0x01000040 -n "U-Boot 2022.10-24689-gfdfea6b32f-dirty for de10-nano board" -d u-boot.bin u-boot.img >/dev/null  && cat /dev/null

  

  cp dts/dt.dtb u-boot.dtb

  

  ./tools/mkimage -A arm -T firmware -C none -O u-boot -a 0x01000040 -e 0x01000040 -n "U-Boot 2022.10-24689-gfdfea6b32f-dirty for de10-nano board"\

   -d u-boot.bin u-boot-dtb.img >/dev/null  && cat /dev/null

   

  arm-none-eabi-objcopy -I binary -O binary --gap-fill=0x0 --pad-to=0x10000 spl/u-boot-spl.sfp spl/u-boot-spl.sfp 

    && cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp spl/u-boot-spl.sfp spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ;

  

   cat spl/u-boot-splx4.sfp u-boot.img > u-boot-with-spl.sfp 

   || rm -f u-boot-with-spl.sfp

   

  ./scripts/check-config.sh u-boot.cfg ./scripts/config_whitelist.txt .

  

  ./scripts/check-of.sh .config ./scripts/of_allowlist.txt

User interface test verification part 24

MORE TOOLCHAIN FUN AND  GAMES

I have six ways to make U-boot, three cross compiler chains and two versions of U-boot source. The older SOC_EDS (System on a Chip Embedded Design Suite), we will call A, a version of Gnu for Ubuntu for ARM chip cross compilation we term B, and a separately downloaded ARM GNU cross compilation chain as C to round out the ways that we can compile assemble and link code. The two source versions are the latest official U-Boot source plus some Altera and DE10 modified source I found on Github.

I tried the Ubuntu chain, setting up both of the source code directories to make with these tools. I did bump into a well know flaw where the device tree compiler DTC gets errors on duplicate definitions of a global variable YYLLOC but deleting one of them in the source is the workaround. I then found the GCC compiler complaining about a parameter passed to it, -march=armv5, which it didn't know how to support. 

My chip should be the armv7-a architecture level since they implemented Cortex A7 processors on the chip. The configuration process should have set this up to build for the A7 processors, I can see the settings in the related configuration files, but when it drops into the lib subdirectory to compile libraries it somehow lost the architecture setting and picked armV5. This could well be the reason that the code doesn't successfully execute to the point of issuing the welcome banner on the console. 

Apparently the two other toolchains do support armV5, issue no messages but build defective code. What this happens is the subject of forensic investigation. U-boot source consists of many hundreds of files and quite a few interlocked Makefiles, thus this is not trivial to debug. 

I attempted to set up a user gcc override, passing in the -march=armv7 parameter but then ran into some errors in the assembler with instructions that didn't match the architecture. Setting it as -march=armv7-a solved those problems. However, when it was time to link SPL, the preloader, it specified a file eabi_compat.o that is needed for certain toolchains (per the comments in its source code) but was not set up for this build. Toolchain B will not work with the official repository. 

I shifted to use the external toolchain C with the official repository, but overriding the -march=armv7-a parameter. This built with no error messages but once again the card won't boot on the DE10-Nano board. 

I did a quick test using chain A just to prove to myself that even with the -march=armv7-a flag, it will sit on the board doing absolutely nothing. In desperation I looked for another toolchain - the embedded Cortex compiler from ARM - which we will call toolchain D.  Absolutely the same results - no signs of life.

User interface test verification part 23

CLUE TO BE CHASED

After interminable permutations of configuring the U-boot and testing I was looking very closely at the SPL (preloader) since that is what should execute to the point that see messages on the console, but it does not. In the directory where the SPL is built a noticed a subdirectory DTS and looked into it.

There is a device tree blob in there, dt-spl.dtb, which when I converted it to source format had no entries at all describing the SDRAM on the board. Without RAM, the SPL will fail quickly. It runs from some limited memory on the board, initializes the regular RAM and copies itself to RAM to continue. If the RAM configuration is incorrect then SPL cannot get very far.

This sounds like the root cause of the completely silent behavior of every SPL I generate, regardless of which of the newer U-boot source versions I use. I will dig into how this is generated during the make process and see if there is a missing file or a failure I can detect somewhere in this godawful toolchain. 

Somehow I detect that absolutely NOBODY tried to generate U-Boot for the Terasic DE10-Nano board in recent years, in spite of Intel having changed their embedded generation process and tools many many times and in spite of many newer versions of U-boot having been released. Nobody responsible or cared enough to try. Since almost every user of these boards that posts videos or blogs simply follow the reference examples exactly, they don't have to address U-boot and therefore don't stumble over the problem.

User interface test verification part 22

 PROBLEMS WITH SPL UNDOUBTEDLY DUE TO ONE OR MORE OF THESE

There is a subset of all the U-Boot configuration choices that affect the preloader (SPL) and that is where I will concentrate since we don't get even the first welcome banner from SPL. Here is the list for one of the U-boot versions I am working with:

#define CONFIG_ARCH_EARLY_INIT_R 1

#define CONFIG_ARCH_FIXUP_FDT_MEMORY 1

#define CONFIG_ARCH_MISC_INIT 1

#define CONFIG_ARCH_SOCFPGA 1

#define CONFIG_ARCH_SUPPORTS_LTO 1

#define CONFIG_ARM 1

#define CONFIG_ARM_ASM_UNIFIED 1

#define CONFIG_ARP_TIMEOUT 5000

#define CONFIG_AUTOBOOT 1

#define CONFIG_AUTO_COMPLETE 1

#define CONFIG_BAUDRATE 115200

#define CONFIG_BLK 1

#define CONFIG_BLOCK_CACHE 1

#define CONFIG_BOARDDIR board/terasic/de10-nano

#define CONFIG_BOOTDELAY 2

#define CONFIG_BOOTDEV_ETH 1

#define CONFIG_BOOTM_EFI 1

#define CONFIG_BOOTMETH_DISTRO 1

#define CONFIG_BOOTMETH_DISTRO_PXE 1

#define CONFIG_BOOTMETH_EFILOADER 1

#define CONFIG_BOOTMETH_GLOBAL 1

#define CONFIG_BOOTMETH_VBE 1

#define CONFIG_BOOTMETH_VBE_SIMPLE 1

#define CONFIG_BOOTM_LINUX 1

#define CONFIG_BOOTM_NETBSD 1

#define CONFIG_BOOTM_PLAN9 1

#define CONFIG_BOOTM_RTEMS 1

#define CONFIG_BOOTM_VXWORKS 1

#define CONFIG_BOOTP_BOOTPATH 1

#define CONFIG_BOOTP_DNS 1

#define CONFIG_BOOTP_GATEWAY 1

#define CONFIG_BOOTP_HOSTNAME 1

#define CONFIG_BOOTP_MAX_ROOT_PATH_LEN 64

#define CONFIG_BOOTP_PXE 1

#define CONFIG_BOOTP_PXE_CLIENTARCH 0x15

#define CONFIG_BOOTP_SUBNETMASK 1

#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7"

#define CONFIG_BOOTSTAGE_STASH_ADDR 0x0

#define CONFIG_BOOTSTAGE_STASH_SIZE 0x1000

#define CONFIG_BOOTSTD 1

#define CONFIG_BOUNCE_BUFFER 1

#define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp"

#define CONFIG_CACHE 1

#define CONFIG_CADENCE_QSPI 1

#define CONFIG_CC_HAS_ASM_INLINE 1

#define CONFIG_CC_IS_GCC 1

#define CONFIG_CC_OPTIMIZE_FOR_SIZE 1

#define CONFIG_CHARSET 1

#define CONFIG_CLANG_VERSION 0

#define CONFIG_CLOCKS 1

#define CONFIG_CMD_ASKENV 1

#define CONFIG_CMD_BDI 1

#define CONFIG_CMD_BLOCK_CACHE 1

#define CONFIG_CMD_BOOTD 1

#define CONFIG_CMD_BOOTEFI 1

#define CONFIG_CMD_BOOTEFI_BOOTMGR 1

#define CONFIG_CMD_BOOTEFI_HELLO_COMPILE 1

#define CONFIG_CMD_BOOTFLOW 1

#define CONFIG_CMD_BOOTM 1

#define CONFIG_CMD_BOOTP 1

#define CONFIG_CMD_BOOTZ 1

#define CONFIG_CMD_CACHE 1

#define CONFIG_CMD_CONSOLE 1

#define CONFIG_CMD_CRC32 1

#define CONFIG_CMD_DFU 1

#define CONFIG_CMD_DHCP 1

#define CONFIG_CMD_DM 1

#define CONFIG_CMD_ECHO 1

#define CONFIG_CMD_EDITENV 1

#define CONFIG_CMD_ELF 1

#define CONFIG_CMD_ENV_EXISTS 1

#define CONFIG_CMD_EXPORTENV 1

#define CONFIG_CMD_EXT2 1

#define CONFIG_CMD_EXT4 1

#define CONFIG_CMD_EXT4_WRITE 1

#define CONFIG_CMD_FAT 1

#define CONFIG_CMD_FDT 1

#define CONFIG_CMD_FPGA 1

#define CONFIG_CMD_FS_GENERIC 1

#define CONFIG_CMD_GO 1

#define CONFIG_CMD_GPIO 1

#define CONFIG_CMD_GREPENV 1

#define CONFIG_CMD_I2C 1

#define CONFIG_CMD_IMI 1

#define CONFIG_CMD_IMPORTENV 1

#define CONFIG_CMD_ITEST 1

#define CONFIG_CMDLINE 1

#define CONFIG_CMDLINE_EDITING 1

#define CONFIG_CMD_LOADB 1

#define CONFIG_CMD_LOADS 1

#define CONFIG_CMD_MDIO 1

#define CONFIG_CMD_MEMORY 1

#define CONFIG_CMD_MII 1

#define CONFIG_CMD_MMC 1

#define CONFIG_CMD_MTDPARTS 1

#define CONFIG_CMD_NET 1

#define CONFIG_CMD_NFS 1

#define CONFIG_CMD_PART 1

#define CONFIG_CMD_PING 1

#define CONFIG_CMD_PXE 1

#define CONFIG_CMD_RANDOM 1

#define CONFIG_CMD_RUN 1

#define CONFIG_CMD_SAVEENV 1

#define CONFIG_CMD_SETEXPR 1

#define CONFIG_CMD_SF 1

#define CONFIG_CMD_SLEEP 1

#define CONFIG_CMD_SOURCE 1

#define CONFIG_CMD_SPI 1

#define CONFIG_CMD_SYSBOOT 1

#define CONFIG_CMD_TFTPBOOT 1

#define CONFIG_CMD_USB 1

#define CONFIG_CMD_USB_MASS_STORAGE 1

#define CONFIG_CMD_XIMG 1

#define CONFIG_COUNTER_FREQUENCY 0

#define CONFIG_CPU_V7A 1

#define CONFIG_CRC32 1

#define CONFIG_CRC32_VERIFY 1

#define CONFIG_CREATE_ARCH_SYMLINK 1

#define CONFIG_CUSTOM_SYS_INIT_SP_ADDR 0x800000

#define CONFIG_DEFAULT_DEVICE_TREE "socfpga_cyclone5_de10_nano"

#define CONFIG_DEFAULT_FDT_FILE "socfpga_cyclone5_de10_nano.dtb"

#define CONFIG_DEFAULT_SPI_BUS 0

#define CONFIG_DEFAULT_SPI_MODE 0x0

#define CONFIG_DESIGNWARE_SPI 1

#define CONFIG_DESIGNWARE_WATCHDOG 1

#define CONFIG_DEVICE_TREE_INCLUDES ""

#define CONFIG_DFU 1

#define CONFIG_DFU_MMC 1

#define CONFIG_DFU_OVER_USB 1

#define CONFIG_DISPLAY_BOARDINFO 1

#define CONFIG_DISPLAY_CPUINFO 1

#define CONFIG_DISTRO_DEFAULTS 1

#define CONFIG_DM 1

#define CONFIG_DM_DEVICE_REMOVE 1

#define CONFIG_DM_DEV_READ_INLINE 1

#define CONFIG_DM_ETH 1

#define CONFIG_DM_EVENT 1

#define CONFIG_DM_GPIO 1

#define CONFIG_DM_I2C 1

#define CONFIG_DM_MMC 1

#define CONFIG_DM_RESET 1

#define CONFIG_DM_SEQ_ALIAS 1

#define CONFIG_DM_SERIAL 1

#define CONFIG_DM_SPI 1

#define CONFIG_DM_SPI_FLASH 1

#define CONFIG_DM_USB 1

#define CONFIG_DM_WARN 1

#define CONFIG_DOS_PARTITION 1

#define CONFIG_DW_ALTDESCRIPTOR 1

#define CONFIG_DWAPB_GPIO 1

#define CONFIG_DW_WDT_CLOCK_KHZ 25000

#define CONFIG_EFI_DEVICE_PATH_TO_TEXT 1

#define CONFIG_EFI_DEVICE_PATH_UTIL 1

#define CONFIG_EFI_DT_FIXUP 1

#define CONFIG_EFI_EBBR_2_0_CONFORMANCE 1

#define CONFIG_EFI_ECPT 1

#define CONFIG_EFI_GRUB_ARM32_WORKAROUND 1

#define CONFIG_EFI_LOADER 1

#define CONFIG_EFI_LOADER_HII 1

#define CONFIG_EFI_LOAD_FILE2_INITRD 1

#define CONFIG_EFI_PLATFORM_LANG_CODES "en-US"

#define CONFIG_EFI_SETUP_EARLY 1

#define CONFIG_EFI_UNICODE_CAPITALIZATION 1

#define CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2 1

#define CONFIG_EFI_VAR_BUF_SIZE 16384

#define CONFIG_EFI_VARIABLE_FILE_STORE 1

#define CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK 1

#define CONFIG_ENV_IS_IN_MMC 1

#define CONFIG_ENV_MAX_ENTRIES 512

#define CONFIG_ENV_MIN_ENTRIES 64

#define CONFIG_ENV_OFFSET 0x4400

#define CONFIG_ENV_SIZE 0x2000

#define CONFIG_ENV_SOURCE_FILE ""

#define CONFIG_ENV_SUPPORT 1

#define CONFIG_ENV_VARS_UBOOT_CONFIG 1

#define CONFIG_ERR_PTR_OFFSET 0xfffec000

#define CONFIG_ETH 1

#define CONFIG_ETH_DESIGNWARE 1

#define CONFIG_ETH_DESIGNWARE_SOCFPGA 1

#define CONFIG_EVENT 1

#define CONFIG_EVENT_DYNAMIC 1

#define CONFIG_EXPERT 1

#define CONFIG_EXT4_WRITE 1

#define CONFIG_FAT_WRITE 1

#define CONFIG_FIT 1

#define CONFIG_FIT_EXTERNAL_OFFSET 0x0

#define CONFIG_FIT_FULL_CHECK 1

#define CONFIG_FIT_PRINT 1

#define CONFIG_FPGA 1

#define CONFIG_FPGA_ALTERA 1

#define CONFIG_FPGA_SOCFPGA 1

#define CONFIG_FS_EXT4 1

#define CONFIG_FS_FAT 1

#define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536

#define CONFIG_GCC_VERSION 110201

#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5

#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525

#define CONFIG_GENERATE_SMBIOS_TABLE 1

#define CONFIG_GICV2 1

#define CONFIG_GPIO 1

#define CONFIG_GPIO_EXTRA_HEADER 1

#define CONFIG_GZIP 1

#define CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR 1

#define CONFIG_HASH 1

#define CONFIG_HAS_THUMB2 1

#define CONFIG_HAS_VBAR 1

#define CONFIG_HAVE_BLOCK_DEVICE 1

#define CONFIG_HAVE_PRIVATE_LIBGCC 1

#define CONFIG_HAVE_SYS_TEXT_BASE 1

#define CONFIG_HUSH_PARSER 1

#define CONFIG_I2C 1

#define CONFIG_IDENT_STRING ""

#define CONFIG_IMX_CONTAINER_CFG ""

#define CONFIG_IMX_DCD_ADDR 0x00910000

#define CONFIG_INPUT 1

#define CONFIG_L2X0_CACHE 1

#define CONFIG_LEGACY_IMAGE_FORMAT 1

#define CONFIG_LIB_ELF 1

#define CONFIG_LIB_RAND 1

#define CONFIG_LIB_UUID 1

#define CONFIG_LINKER_LIST_ALIGN 4

#define CONFIG_LMB 1

#define CONFIG_LMB_MAX_REGIONS 8

#define CONFIG_LMB_USE_MAX_REGIONS 1

#define CONFIG_LOCALVERSION ""

#define CONFIG_LOCALVERSION_AUTO 1

#define CONFIG_LOGLEVEL 4

#define CONFIG_MD5 1

#define CONFIG_MENU 1

#define CONFIG_MII 1

#define CONFIG_MKIMAGE_DTC_PATH "dtc"

#define CONFIG_MMC 1

#define CONFIG_MMC_DW 1

#define CONFIG_MMC_DW_SOCFPGA 1

#define CONFIG_MMC_HW_PARTITIONING 1

#define CONFIG_MMC_QUIRKS 1

#define CONFIG_MMC_VERBOSE 1

#define CONFIG_MMC_WRITE 1

#define CONFIG_MTD 1

#define CONFIG_MTDIDS_DEFAULT "nor0=ff705000.spi.0"

#define CONFIG_MTDPARTS_DEFAULT ""

#define CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ 0x8000

#define CONFIG_NET 1

#define CONFIG_NETDEVICES 1

#define CONFIG_NET_RETRY_COUNT 5

#define CONFIG_NET_TFTP_VARS 1

#define CONFIG_NFS_TIMEOUT 2000

#define CONFIG_NR_DRAM_BANKS 1

#define CONFIG_OF_CONTROL 1

#define CONFIG_OF_LIBFDT 1

#define CONFIG_OF_LIBFDT_ASSUME_MASK 0x0

#define CONFIG_OF_LIST "socfpga_cyclone5_de10_nano"

#define CONFIG_OF_REAL 1

#define CONFIG_OF_SEPARATE 1

#define CONFIG_OF_SPL_REMOVE_PROPS "pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupts"

#define CONFIG_OF_TRANSLATE 1

#define CONFIG_PARTITIONS 1

#define CONFIG_PARTITION_UUIDS 1

#define CONFIG_PHY_GIGE 1

#define CONFIG_PHYLIB 1

#define CONFIG_PHY_MICREL 1

#define CONFIG_PHY_MICREL_KSZ90X1 1

#define CONFIG_PHY_RESET_DELAY 0

#define CONFIG_PLATFORM_ELFENTRY "_start"

#define CONFIG_POWER 1

#define CONFIG_PRINTF 1

#define CONFIG_PXE_UTILS 1

#define CONFIG_RAM 1

#define CONFIG_REGEX 1

#define CONFIG_REGMAP 1

#define CONFIG_REQUIRE_SERIAL_CONSOLE 1

#define CONFIG_RESET_SOCFPGA 1

#define CONFIG_SAVEENV 1

#define CONFIG_SDP_LOADADDR 0x0

#define CONFIG_SERIAL 1

#define CONFIG_SERIAL_PRESENT 1

#define CONFIG_SERVERIP_FROM_PROXYDHCP_DELAY_MS 100

#define CONFIG_SF_DEFAULT_BUS 0

#define CONFIG_SF_DEFAULT_CS 0

#define CONFIG_SF_DEFAULT_MODE 0x0

#define CONFIG_SF_DEFAULT_SPEED 1000000

#define CONFIG_SHA1 1

#define CONFIG_SHA256 1

#define CONFIG_SIMPLE_BUS 1

#define CONFIG_SPI 1

#define CONFIG_SPI_FLASH 1

#define CONFIG_SPI_FLASH_MTD 1

#define CONFIG_SPI_FLASH_SMART_HWCAPS 1

#define CONFIG_SPI_FLASH_UNLOCK_ALL 1

#define CONFIG_SPI_FLASH_USE_4K_SECTORS 1

#define CONFIG_SPI_MEM 1

#define CONFIG_SPL 1

#define CONFIG_SPL_ALTERA_SDRAM 1

#define CONFIG_SPL_BANNER_PRINT 1

#define CONFIG_SPL_BLK 1

#define CONFIG_SPL_BUILD 1

#define CONFIG_SPL_CACHE 1

#define CONFIG_SPL_CRC32 1

#define CONFIG_SPL_DM 1

#define CONFIG_SPL_DM_I2C 1

#define CONFIG_SPL_DM_INLINE_OFNODE 1

#define CONFIG_SPL_DM_MMC 1

#define CONFIG_SPL_DM_RESET 1

#define CONFIG_SPL_DM_SERIAL 1

#define CONFIG_SPL_DM_SPI 1

#define CONFIG_SPL_DM_SPI_FLASH 1

#define CONFIG_SPL_DM_USB 1

#define CONFIG_SPL_DOS_PARTITION 1

#define CONFIG_SPL_FRAMEWORK 1

#define CONFIG_SPL_IMAGE "spl/u-boot-spl.bin"

#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"

#define CONFIG_SPL_LEGACY_IMAGE_FORMAT 1

#define CONFIG_SPL_LIBCOMMON_SUPPORT 1

#define CONFIG_SPL_LIBDISK_SUPPORT 1

#define CONFIG_SPL_LIBGENERIC_SUPPORT 1

#define CONFIG_SPL_LOGLEVEL 4

#define CONFIG_SPL_MAX_SIZE 0x0

#define CONFIG_SPL_MMC 1

#define CONFIG_SPL_NO_BSS_LIMIT 1

#define CONFIG_SPL_OF_CONTROL 1

#define CONFIG_SPL_OF_LIBFDT 1

#define CONFIG_SPL_OF_LIBFDT_ASSUME_MASK 0xff

#define CONFIG_SPL_OF_LIST "socfpga_cyclone5_de10_nano"

#define CONFIG_SPL_OF_REAL 1

#define CONFIG_SPL_PAD_TO 0x10000

#define CONFIG_SPL_PARTITIONS 1

#define CONFIG_SPL_PAYLOAD "u-boot.bin"

#define CONFIG_SPL_PRINTF 1

#define CONFIG_SPL_RAM 1

#define CONFIG_SPL_RAM_DEVICE 1

#define CONFIG_SPL_RAM_SUPPORT 1

#define CONFIG_SPL_RAW_IMAGE_SUPPORT 1

#define CONFIG_SPL_SERIAL 1

#define CONFIG_SPL_SERIAL_PRESENT 1

#define CONFIG_SPL_SHA1 1

#define CONFIG_SPL_SHA256 1

#define CONFIG_SPL_SIMPLE_BUS 1

#define CONFIG_SPL_SIZE_LIMIT 0x10000

#define CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK 0x200

#define CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD 1

#define CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC 1

#define CONFIG_SPL_SPI 1

#define CONFIG_SPL_SPI_FLASH_SUPPORT 1

#define CONFIG_SPL_SPI_FLASH_TINY 1

#define CONFIG_SPL_SPI_LOAD 1

#define CONFIG_SPL_SPRINTF 1

#define CONFIG_SPL_STACK 0x0

#define CONFIG_SPL_STACK_R 1

#define CONFIG_SPL_STACK_R_ADDR 0x00800000

#define CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN 0x100000

#define CONFIG_SPL_STRTO 1

#define CONFIG_SPL_SYS_MALLOC_F_LEN 0x800

#define CONFIG_SPL_SYS_MALLOC_SIMPLE 1

#define CONFIG_SPL_SYSRESET 1

#define CONFIG_SPL_SYS_STACK_F_CHECK_BYTE 0xaa

#define CONFIG_SPL_SYS_THUMB_BUILD 1

#define CONFIG_SPL_TARGET ""

#define CONFIG_SPL_TEXT_BASE 0xFFFF0000

#define CONFIG_SPL_USE_ARCH_MEMCPY 1

#define CONFIG_SPL_USE_ARCH_MEMSET 1

#define CONFIG_SPL_USE_TINY_PRINTF 1

#define CONFIG_SPL_WATCHDOG 1

#define CONFIG_SPRINTF 1

#define CONFIG_STACK_SIZE 0x1000000

#define CONFIG_STRTO 1

#define CONFIG_SUPPORT_ACPI 1

#define CONFIG_SUPPORT_OF_CONTROL 1

#define CONFIG_SUPPORT_RAW_INITRD 1

#define CONFIG_SUPPORT_SPL 1

#define CONFIG_SYS_ARCH "arm"

#define CONFIG_SYS_ARM_ARCH 7

#define CONFIG_SYS_ARM_CACHE_CP15 1

#define CONFIG_SYS_ARM_CACHE_WRITEBACK 1

#define CONFIG_SYS_ARM_MMU 1

#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_SYS_BOARD "de10-nano"

#define CONFIG_SYS_BOOTM_LEN 0x800000

#define CONFIG_SYS_BOOT_RAMDISK_HIGH 1

#define CONFIG_SYS_CACHELINE_SIZE 64

#define CONFIG_SYS_CACHE_SHIFT_6 1

#define CONFIG_SYS_CBSIZE 1024

#define CONFIG_SYS_CLK_FREQ 0

#define CONFIG_SYSCON 1

#define CONFIG_SYS_CONFIG_NAME "socfpga_de10_nano"

#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1

#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1

#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1

#define CONFIG_SYS_CPU "armv7"

#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1000000

#define CONFIG_SYS_DFU_MAX_FILE_SIZE 0x1000000

#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 0

#define CONFIG_SYS_FDT_PAD 0x3000

#define CONFIG_SYS_HZ 1000

#define CONFIG_SYS_I2C_BUS_MAX 4

#define CONFIG_SYS_I2C_DW 1

#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000

#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE

#define CONFIG_SYS_L2_PL310 

#define CONFIG_SYS_LOAD_ADDR 0x01000000

#define CONFIG_SYS_LONGHELP 1

#define CONFIG_SYS_MALLOC_CLEAR_ON_INIT 1

#define CONFIG_SYS_MALLOC_F 1

#define CONFIG_SYS_MALLOC_F_LEN 0x2000

#define CONFIG_SYS_MALLOC_LEN 0x4000000

#define CONFIG_SYS_MAXARGS 32

#define CONFIG_SYS_MEM_TOP_HIDE 0x0

#define CONFIG_SYS_MMC_ENV_DEV 0

#define CONFIG_SYS_MMC_ENV_PART 0

#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256

#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET 0x0

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 0x1

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE 0xa2

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION 1

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE 1

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 1

#define CONFIG_SYS_NS16550 1

#define CONFIG_SYS_PBSIZE 1044

#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS

#define CONFIG_SYS_PROMPT "=> "

#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "

#define CONFIG_SYS_RELOC_GD_ENV_ADDR 1

#define CONFIG_SYSRESET 1

#define CONFIG_SYSRESET_CMD_RESET 1

#define CONFIG_SYSRESET_SOCFPGA 1

#define CONFIG_SYS_RX_ETH_BUFFER 4

#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1

#define CONFIG_SYS_SOC "socfpga"

#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000

#define CONFIG_SYS_SRAM_BASE 0x0

#define CONFIG_SYS_SRAM_SIZE 0x0

#define CONFIG_SYS_TEXT_BASE 0x01000040

#define CONFIG_SYS_THUMB_BUILD 1

#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS

#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)

#define CONFIG_SYS_TIMER_COUNTS_DOWN 

#define CONFIG_SYS_TIMER_RATE 25000000

#define CONFIG_SYS_VENDOR "terasic"

#define CONFIG_SYS_XTRACE 1

#define CONFIG_TARGET_SOCFPGA_CYCLONE5 1

#define CONFIG_TARGET_SOCFPGA_GEN5 1

#define CONFIG_TARGET_SOCFPGA_TERASIC_DE10_NANO 1

#define CONFIG_TFTP_BLOCKSIZE 1468

#define CONFIG_TFTP_WINDOWSIZE 1

#define CONFIG_TIMESTAMP 1

#define CONFIG_TOOLS_CRC32 1

#define CONFIG_TOOLS_FIT 1

#define CONFIG_TOOLS_FIT_FULL_CHECK 1

#define CONFIG_TOOLS_FIT_PRINT 1

#define CONFIG_TOOLS_FIT_RSASSA_PSS 1

#define CONFIG_TOOLS_FIT_SIGNATURE 1

#define CONFIG_TOOLS_FIT_SIGNATURE_MAX_SIZE 0x10000000

#define CONFIG_TOOLS_FIT_VERBOSE 1

#define CONFIG_TOOLS_LIBCRYPTO 1

#define CONFIG_TOOLS_MD5 1

#define CONFIG_TOOLS_OF_LIBFDT 1

#define CONFIG_TOOLS_SHA1 1

#define CONFIG_TOOLS_SHA256 1

#define CONFIG_TOOLS_SHA384 1

#define CONFIG_TOOLS_SHA512 1

#define CONFIG_USB 1

#define CONFIG_USB_DWC2 1

#define CONFIG_USB_DWC2_BUFFER_SIZE 64

#define CONFIG_USB_FUNCTION_MASS_STORAGE 1

#define CONFIG_USB_GADGET 1

#define CONFIG_USB_GADGET_DOWNLOAD 1

#define CONFIG_USB_GADGET_DUALSPEED 1

#define CONFIG_USB_GADGET_DWC2_OTG 1

#define CONFIG_USB_GADGET_MANUFACTURER "terasic"

#define CONFIG_USB_GADGET_PRODUCT_NUM 0xa4a5

#define CONFIG_USB_GADGET_VBUS_DRAW 2

#define CONFIG_USB_GADGET_VENDOR_NUM 0x0525

#define CONFIG_USB_HOST 1

#define CONFIG_USB_STORAGE 1

#define CONFIG_USE_ARCH_MEMCPY 1

#define CONFIG_USE_ARCH_MEMSET 1

#define CONFIG_USE_PRIVATE_LIBGCC 1

#define CONFIG_VERSION_VARIABLE 1

#define CONFIG_WATCHDOG_TIMEOUT_MSECS 10000

#define CONFIG_ZLIB 1

The documentation for these parameters is only the source code itself. No documentation for U-boot and SPL to describe what these do and how to select the appropriate choices. Anyone see the one(s) that are incorrect?? Let me know.