Testing fully assembled new 1130 MRAM board - read retriggering solved!

TESTING FULLY ASSEMBLED BOARD ON TEST BENCH

I put the finished board on the bench and tested it by triggering a read (rising edge of +Storage Read signal) and watching the sense output lines. I wanted to see multiple 1 bits being emitted for a given read, with the output lines pulled down to ground for 80-100ns for all the bit positions that have a 1 value. There should be one pulse for those bit positions and no retriggering causing subsequent pulses every 800 ns after the first one. 

Everything looked good with this testing, so I moved on to the 1130. I frankly didn't do a lot of detailed testing on the testbench because it was cumbersome to move the probes around. For example, I didn't try writes nor changing the address bits to verify that different locations preserved their contents independently. 

TESTING FULLY ASSEMBLED BOARD ON 1130

The PCB was connected to the 1130 system and everything was powered up. I used the rotary mode control to set the machine to Display mode, where each push of the Prog Start button will drive a storage cycle - a read followed by a write. That will raise the +Storage Read line at first which is what will allow me to watch the sense output pulses. 

Having first set the mode switch to Load mode, I loaded memory with various values then turned to Display mode. I want to watch the output pulses on selected bit positions, seeing only a single pulse not spuriously retriggered pulses. I also wanted the value latched into the Storage Buffer Register (SBR) to match what I had stored. 

Instead I saw somewhat random bits showing up in the SBR and the scope pattern for the sense output pulses didn't make sense. I was seeing two 80-100 ns pulses, one shortly after +Storage Read went high and then another at the proper time. I didn't see that occurring on the testbench.

FOUND BAD CONNECTION ON WRITE TIMER CHIP

I realized that in most cases, the same data patterns came out for various addresses as I did Display operations. I was not able to store any different data patterns into RAM, but it was returning deterministically (to at least a superficial level of testing). I then discovered a pin on the write timer chain (first of two timer chips) that was not soldered reliably to the pad. After correction, I could write patterns into RAM. 

ORIGINAL RETRIGGERING ISSUE FIXED

I was not seeing any spurious retriggering beyond the duration of the read portion (1.8 uS) of a storage access, which means that the original bedeviling problem has been mastered. It was kind of a stab in the dark to add in the separate transistors to drive the sense output pulses instead of using the open collector logic gate that produced the pulse. 

I then had a eureka moment when seeing the pulses occurring very soon after the start of the +Storage Read high signal. I noticed that a second pulse at the correct time was happening whenever the board was returning  a 1 bit in that position, while the first pulse seemed unrelated. 

EUREKA MOMENT

Realization rolled over me at that moment. I realized that my sense output pulse, which is a transistor pulling a line down to ground for 80=100 nanoseconds, wasn't connected only to the flipflop that would turn on for the falling edge. There were multiple gates connected together in what IBM calls a wired-OR. That is all the output wires from the various gates are just shorted together - with each of them acting as an open collector driver - so that any of them could activate the flipflop. It was not only a sense output from core memory that turns on the flipflop.

What I was seeing was other gates hooked to the flipflop creating a setting pulse for some other reason. The various gates that produce pulses to set the Storage Buffer Register bit position to 1 are:

• IO bit is gated to B register (SBR) - peripheral  controller drives this
• I (Instruction Address Register) is gated to B 
• A (Accumulator Register) is gated to B
• Core sense output pulses sets B

I don't know what would produce one of those pulses during the T0 clock phase of the read cycle, where I was seeing the pulse on the 1130 side. The gates above should only operate if the machine is trying to store something in a memory location - the IAR, Accumulator or an IO controller word - which should not be happening here.

My next round of testing will focus on what is causing this T0 gating to the SBR. I don't understand why this would happen during a Display mode storage cycle. Either this is a defect somewhere in the 1130 that needs correction or it is a normal behavior that does not cause problems when IBM core memory is used. 

These pulses are pulling the input of the flipflop called the "AC trigger" down to ground, discharging a capacitor that was charged up by the enabling line to the AC trigger. If the capacitor is discharged fast enough and for long enough, the flipflop changes state. It requires about 8ma of current sinking to achieve the setting of the flipflop, times each bit position that has it flipflop set. That is up to 18 flipflops (for a word of all 1 bits).

It appears that something occurring during the discharge was being injected back into the 1130 MRAM board through the supposedly open drain NAND chips. Probably a negative excursion of the line which pulled down the VCC of my board enough to cause the ringing and spurious retriggering. The replacement of the NAND chips with an AND followed by a discrete transistor seemed to resolve this as the transistor could handle the short reverse voltages without any interaction with my VCC and ground planes. 

SOME MANUAL OPERATIONS TESTING THE BOARD

Using the LOAD and DISPLAY modes of the 1130, I was able to put in contents to specific locations and read them back. This is a mode where you take a single storage cycle, pushing the Prog Start button to display or load at the current address. These seemed to be working properly.

I then used the STORAGE LOAD and STORAGE DISPLAY switches on the CE (Customer Engineer) panel to load patterns to all memory locations in a loop or to loop through reading all memory locations. Storing a value of x0000 worked correctly, always returning zeroes. However, when I set the pattern to something else, such as xFFFF, the load appeared to be working but when displaying I got back variable random data and parity errors. 

Since parity is generated on my board based on what is read back from the RAM chip, the only way to see a parity error on the 1130 is if the data being latched into the SBR is not what was read from the chip. This suggests a timing issue or another problem that may be happening during continuous successive storage cycles such as the looping of STORAGE LOAD. 

During my next round of testing, I will examine what is happening during continuous storage cycles and look for defects either in my design, the current board or the 1130. 

Testing attempt on new 1130MRAM board

PCB AND STENCIL FABBED BY JLCPCB.COM

I used my long time PCB fabrication house, JLCPCB.COM, to build the four layer board. Once again it was easy to upload the design, configure the board to my specs, pay and watch the progress as it was manufactured. I also uploaded the design to create a stencil for the top layer of the PCB.

The stencil came in a larger separate shipping package with wood boards sandwiching the thin aluminum part. My PCBs came in a smaller blue box, shrink wrapped and padded. I selected DHL two day shipment. The parts were made on the promised schedule and the boxes arrived one day earlier than expected. 

TESTING OF PARTIALLY ASSEMBLED BOARD WITH TEST BENCH

I produced a rising edge on +Storage Read and watched the sense output lines for the output pulse. The goal is to see pulses on all eighteen output pins. Further, there should be one and only one output pulse per rising edge of the input trigger. 

The bits were all treated as if they were 0 value, thus no output pulses. I did see the timer chain output pulse. Based on this, I believe have to assemble the board completely in order to test its behavior properly. 

BUILDING THE FULL BOARD

I removed the components from the prior board and installed them on the new board. For each, I used a section of the stencil to lay down solder paste over the solder pads, placed the part atop the board and used my heat rework tool to melt the solder. 

I also had to harvest all the decoupling capacitors from the backside of the old board and install them on the new PCB. One disappeared into the mists as I tried to install it, snapping off the tweezers with which I was holding it, but I had spare capacitors on hand. 

TESTING CONNECTIVITY OF ALL PINS

I used by PCBite test platform to hold the PCB while I placed probes on each pin in turn, putting a probe on a remote pin that should be connected to the same net. It took a while to beep out several hundred pins but the time was well invested as it gave me confidence that I didn't have any bad solder joints. 

Interim method won't work; assembling new PCB

FASTER 2N2369A TRANSISTORS TRIED

The same setup with the square wave generator was used with the faster 2N2369A transistor and I did see a substantial improvement, with the pair of transistors operating to about 4.4MHz although the waveform was very distorted. The first transistor signal was better than the second, where irregularities were multiplied. 

The circuit on the new PCB has a single transistor driven by an AND gate but the interim method has a NAND gate on the old board so I needed to invert its output with a first transistor before driving the second one. The other issue is that I need the special board to intercept the signals on the ribbon cable, wires tacked on and a breadboard to host the transistors. 

Turns out that the capacitance and other consequences of the all the above will cut down on the max frequency I could handle. The new PCB with its short controlled traces will undoubtedly operate faster - hopefully up to the 10-12MHz rate of the memory system. 

BUILDING NEW PCB IN STAGES

I received the new PCBs, the stencil, and the parts while I was on a roadtrip to pick up a 3179 color terminal in Atlanta. I decided to assemble only the components I need to determine if my approach will stop the spurious retriggering issues. Since this occurs when many bits of a word have a 1 value, causing many of the sense output lines to be pulsed at the same time, I prepared the PCB to produce that situation when the 1130 attempts a read. 

I had to install the connector pins, the power regulator, the five AND gates, the 18 fast transistors, the two timer chips and the logic IC, plus resistors and capacitors. These will produce the timer pulse when the +Storage Read signal has a rising edge, causing the transistors to pull the output line down to ground for any bit position where the input appears to be a logic high (1). 

I am hoping that the AND gate will treat the floating input pins as a logic high, thus generating an output pulse when the timer pulse occurs. The previous NAND chips acted that way. If it does. then the partially assembled board will emit a pulse on all eighteen output pins, the maximum stressing condition for retriggering. 

The IBM 1130 can be connected to the PCB by the three ribbon cables. When the 1130 issues a read (+Storage Read goes high) and +Storage Use is high (floating pin is treated as a high), the board will produce 80-100 nanosecond pulses about 800 ns after the rising edge of the read request. 

BIG FAN OF USING A STENCIL

The stencil is a thin bit of aluminum with holes cut into it in the shape of every solder pad. It is held on the PCB and solder paste is forced into the holes with a putty spreader. The stencil is pulled up, the components are placed on the board and hot air is used to melt the solder and bond the pins to the pads. 

I used tin shears to but the stencil, removing each section as I soldered down components. Otherwise the previously installed parts would block the stencil from laying flat on the PCB. This means I can't use it for additional PCBs - a one time use - but I will happily order another once this board is fully tested and worth duplicating. 

Attempting to test the discrete transistor method of resolving the 1130 MRAM retriggering

NEW APPROACH IN LATEST PCB DESIGN

The prior boards used an open collector NAND gate to generate the 80-100 ns pulse that represents a 1 bit at a given bit position in the addressed word of memory. When several positions had a 1 value, spurious retriggering would occur which produced a string of pulses rather than the single pulse that should be emitted during a read cycle. 

The new approach places a discrete transistor as the open collector driver of the pulse, after being fed by an AND gate (since the transistor inverts, the NAND logic function must become an AND). This isolates the current sinking that occurs during the pulse and ensures a pure ground path for that current which comes from the IBM 1130 logic cards for the Storage Buffer Register. 

I selected a transistor with very small delays in order to crisply produce the pulse - BSV52 - but there is no discrete version of this, only surface mount parts. That makes it quite difficult to test out the use of the transistor without having a PCB onto which it will be soldered. 

METHOD TO ATTEMPT A TEST BEFORE THE NEW PCB ARRIVES

Since PCB fabrication takes some time, both for the manufacture and then the shipping, I thought of ways that I could test the theory in the otherwise idle days ahead. I realized that I could intercept the connections and interpose transistors between my existing PCB and the 1130, by repurposing a blank of the old PCB type and two IBM SLT ribbon cables.

The IBM 1130 connects to my 1130 MRAM PCB with three SLT ribbon cables (T1, T3 and T4). My PCB has pins on it that form an SLT male socket into which the connector end will plug. I realized that I could form SLT male sockets on a spare PCB using more pins, then grab the signal on the pads where they would have connected to integrated circuits if the board were fully assembled. 

I will check this out using only cable T4. This delivers the pulses for sense bits 10, 11, 12, 13, 14, 15 and the two parity bits P1 and P2. I will plug cable T4 into the spare PCB position for T1 and plug a spare SLT ribbon cables between the T4 slot of the spare board and the T4 slot of my 1130 MRAM board. Cables T1 and T3 run from the 1130 directly to my PCB.

The spare PCB will have the sense signals from my board arrive on position T1. I will grab the signals with wires tacked onto the IC pads connected to the pins of T1 that I want to intercept. Those signals go to a breadboard with a pair of transistors for each bit position. The first will invert the signal to convert the NAND output of my PCB to an AND output. The second will be the open collector driver of a signal connected to position T4 of the spare board again using IC pads that connect to the relevant pins of the connector. 

BUILDING THE SPARE PCB TO INTERCEPT SIGNALS

I tacked wires on the pads to capture the eight signals from connector T1 and to output signals onto connector T4. I then began installing the gold pins that form the SLT male socket into which the ribbon cables connect. 

However, I ran out of pins and have to wait for additional pins that are on order from Digikey. Meanwhile I can work on the breadboard with transistors and do some testing of the capabilities of the discrete transistors I have on hand. 

BUILDING BREADBOARD WITH PAIRS OF NPN TRANSISTORS

I used a very simple circuit for each bit position I am intercepting. A first NPN transistor has a base resistor of 2K and a 10K pullup resistor on the collector to 3.3V. The input from T1 on the spare PCB needs a pullup to 3.3V as well because my original PCB is open collector, expecting the 1130 side to pull the line to 3V. The second transistor is coupled to the collector of the first by another 2K resistor. The collector is what is hooked up to the T4 side of the spare PCB. 

I had a number of discrete NPN transistors on hand. I tested with both 2N5551 and MPS2222A transistors in pairs. I used a square wave generator as the input and observed the output on my oscilloscope with an added pullup to 3.3V on that probe. 

LIMITATIONS OF THE DISCRETE TRANSISTORS I HAD ON HAND

The 2N5551 mangled the square wave at pretty low frequencies and stopped working at 750 KHz. My pulses are equivalent to more than 10 MHz. This certainly won't work with the 1130 system. 

When I tested the MPS2222A transistors, things got even worse. The transistor only worked up to about 140 KHz and the wave was much more mangled. 

The BSV52 should do the job, with turn on and turn off times of 10 to 12 nanoseconds while the discrete transistor types I used had much longer times. The nearest discrete part I could find that was similarly low in delay is 2N2369 or 2N4449 but these were not on hand. I just bought some from Mouser and will retest in a few days when they arrive.

Ordered new PCB with my original fab to reduce delays

WORKED TO INVOKE SPONSORSHIP OFFER FOR THIS PCB

I uploaded the design files and contacted the marketing department to take them up on the offer. Since I did this just before a weekend it took a couple days to swap emails. I have a pretty small viewership of my blog so I fully understand that they have limits especially with a new relationship. To be fair, US duties and tariffs add to the costs for PCBWAY. 

The first response asked if I could drop the stencil since the project was over their budget. I was unwilling to skip the stencil so I asked if I could pay the incremental cost - including duty would be around $20. The next response did try to accommodate me but by separating the shipments and sending both via Global Direct Shipment which means the PCB and the stencil won't arrive for a few weeks.

DIDN'T WORK OUT FOR THIS PROJECT, SWITCHED BACK TO JLCPCB

I always use Fedex or UPS to receive the products in 3-5 business days not weeks. I have the build time to add to the delay, plus the several days involved in the email exchanges. Based on this, I placed the order with JLCPCB with Fedex delivery, in order to minimize further delays working on the memory project. 

I will still work with PCBWAY, but need to do this with a simpler project, one that can accept longer delays. The current 9" x 4.5" four layer PCB plus the stencil due to all the SMD parts wasn't a good fit. A future smaller, maybe 2 layer part will be a better starting point for the relationship. 

Revised design and producing a new board for 1130 MRAM project

IN ORDER TO CONTROL THE CURRENT SINKING, I MOVED TO DISCRETE TRANSISTORS

Since the bounce is dependent on the number of the sense bits that have a 1 value and thus cause an output pulse, the issue is in the open collector NAND gates, the PCB itself or something the IBM 1130 side is driving into my board. I decided to use a NPN transistor to sink the current from the 1130 to produce the sense pulses - which are negative going pulses from the 3V SLT pullup voltage down to ground. 

The pulses are in the range of 80 nanoseconds in duration, so I had to use a transistor that was fast enough for this, would recover back to 3V quickly and could sink the 8ma I estimate that is pulled to set the 1130 flipflop with a 1 value. I selected the BSV52 from OnSemi. It has turn on and turn off times of 12 and 18 nanoseconds, able to sink more than three times my target current and readily available. 

With the transistor I had to flip the output gate from a quad NAND open drain (74lcx38) type to a quad AND gate (74LVC08A). These use the same TSSOP-14 footprint and pin assignments. 

I redesigned the PCB to introduce the 18 transistors and 18 base resistors between the sense output pins and the quad AND gate. Thus when the read timer goes off with a positive pulse of 80-100 nanoseconds, any RAM bit that is one will cause that AND gate to output an 80-100ns positive pulse. The BSV52 transistor will invert this with its open collector to pull the 1130's 3V sense output line down to ground for 80ns. This will be offset by about 12 nanoseconds but that is well within the wide range of timing that is available to set bits into the 1130 Storage Buffer Register. 

I was very diligent to make sure that the ground plane was uninterrupted except for small cutouts around vias, thus offering a very strong path for the current to sink into the PCB from the transistors and out the heavy stranded wire to the 1130 power system. 

SWITCHING TO NEW FAB WITH PCBWAY

I received an offer from PCBWAY.com to sponsor the PCBs I develop in exchange for my sharing the experience and board quality on this blog. Later when I assemble the new PCB to begin testing, I will share a few paragraphs covering PCBWAY. I took the opportunity to buy an SMD stencil, which should make my soldering much easier.

An SMD stencil is a thin piece of metal that has holes cut in it for every pad. Solder paste is spread across the stencil and is thus only deposited on the pads themselves on the board. My manual method of applying the paste left excess which turned to teeny solder balls that spattered around, while also being inconsistent enough that I couldn't guarantee a good connection of every pin. 

HOPED TO VERIFY THE SOLUTION WORKED BEFORE PRODUCING THE PCB

I wanted to breadboard some transistors to see if that would resolve the issues with spurious retriggering of the timer pulses. That was going to involve my bodging up another PCB blank, then using spare SLT ribbon cables to jumper this special board between my PCB and the 1130 system. I figured out a way to use the blank board to hold pins to form SLT sockets. 

I would be able to form two sockets, to handle eight sense output pins. One socket would connect to cable T4 from the 1130 and the other socket would plug into a jumper cable that is in turn plugged into my current PCB position T4. I would tack wires on pads connected to the pins and then run them to discrete transistors on a perf board. Signal quality wouldn't be great but I could validate the plan to work properly without the retriggering. 

Because the existing PCB has a NAND gate output, I would have to invert the signal with one transistor and then drive the open collector connection with a second. Thus the perf board would have 16 transistors and a bunch of resistors, all tenuously wired to the pads of the special PCB that acts as a pair of SLT connectors. 

However, a similar discrete NPN transistor with these low delay characteristics is obsolete, thus would cost several dollars per transistor and be tossed at the end of the test. The surface mount BSV52 transistors are way too tiny to try to tack on wires to the leads as it would be a very unreliable mess. 

I therefore had to gamble that this will work, ordering the BVS52 transistors and new PCB up front, then assemble it and only then see if the fix works. 

Checking out the low ESR cause for the 1130 MRAM ringing

QUICK VERIFICATION OF THIS THEORY OF A ROOT CAUSE

I soldered a  ohm resistor in series with the 4.7 uF ceramic capacitor. I then tried the board on the 1130 again and observed the operation. 

It failed in the same way as before. Perhaps the regulator itself is bad or I still don't have the Equivalent Series Resistance (ESR) in the stable range. 

I used a quick and dirty hack was to use an external 3.3V power supply after lifting the LD1117 from the circuit. I used heavy stranded wires between the supply and the board. This would let me know immediately if oscillation of the regulator is the root cause of my problems. 

And . . . it is not. The exact same failure mode occurred using a bench supply to power the logic. Arrgh. 

Time for a plan C. I will think on this a while and figure out something else to do that might resolve this problem. I think it is down to three possibilities:

1. The timer chips are either bizarre or defective, but that isn't likely since I see spurious repeats on the write timer chain as well as the read timer chain. 
2. Something in the 1130 side is causing this, some way that I am not understanding. 
3. Something on the PCB is causing this, maybe a combination of the decoupling capacitors and traces, again in a way I am not understanding.

That means my plan C has to be more of a desperation move where I change parts of the design just to see if a different set of parts or different approach avoids the problem.