Ordered new PCB with my original fab to reduce delays

WORKED TO INVOKE SPONSORSHIP OFFER FOR THIS PCB

I uploaded the design files and contacted the marketing department to take them up on the offer. Since I did this just before a weekend it took a couple days to swap emails. I have a pretty small viewership of my blog so I fully understand that they have limits especially with a new relationship. To be fair, US duties and tariffs add to the costs for PCBWAY. 

The first response asked if I could drop the stencil since the project was over their budget. I was unwilling to skip the stencil so I asked if I could pay the incremental cost - including duty would be around $20. The next response did try to accommodate me but by separating the shipments and sending both via Global Direct Shipment which means the PCB and the stencil won't arrive for a few weeks.

DIDN'T WORK OUT FOR THIS PROJECT, SWITCHED BACK TO JLCPCB

I always use Fedex or UPS to receive the products in 3-5 business days not weeks. I have the build time to add to the delay, plus the several days involved in the email exchanges. Based on this, I placed the order with JLCPCB with Fedex delivery, in order to minimize further delays working on the memory project. 

I will still work with PCBWAY, but need to do this with a simpler project, one that can accept longer delays. The current 9" x 4.5" four layer PCB plus the stencil due to all the SMD parts wasn't a good fit. A future smaller, maybe 2 layer part will be a better starting point for the relationship. 

Revised design and producing a new board for 1130 MRAM project

IN ORDER TO CONTROL THE CURRENT SINKING, I MOVED TO DISCRETE TRANSISTORS

Since the bounce is dependent on the number of the sense bits that have a 1 value and thus cause an output pulse, the issue is in the open collector NAND gates, the PCB itself or something the IBM 1130 side is driving into my board. I decided to use a PNP transistor to sink the current from the 1130 to produce the sense pulses - which are negative going pulses from the 3V SLT pullup voltage down to ground. 

The pulses are in the range of 80 nanoseconds in duration, so I had to use a transistor that was fast enough for this, would recover back to 3V quickly and could sink the 8ma I estimate that is pulled to set the 1130 flipflop with a 1 value. I selected the BSV52 from OnSemi. It has turn on and turn off times of 12 and 18 nanoseconds, able to sink more than three times my target current and readily available. 

With the transistor I had to flip the output gate from a quad NAND open drain (74lcx38) type to a quad AND gate (74LVC08A). These use the same TSSOP-14 footprint and pin assignments. 

I redesigned the PCB to introduce the 18 transistors and 18 base resistors between the sense output pins and the quad AND gate. Thus when the read timer goes off with a positive pulse of 80-100 nanoseconds, any RAM bit that is one will cause that AND gate to output an 80-100ns positive pulse. The BSV52 transistor will invert this with its open collector to pull the 1130's 3V sense output line down to ground for 80ns. This will be offset by about 12 nanoseconds but that is well within the wide range of timing that is available to set bits into the 1130 Storage Buffer Register. 

I was very diligent to make sure that the ground plane was uninterrupted except for small cutouts around vias, thus offering a very strong path for the current to sink into the PCB from the transistors and out the heavy stranded wire to the 1130 power system. 

SWITCHING TO NEW FAB WITH PCBWAY

I received an offer from PCBWAY.com to sponsor the PCBs I develop in exchange for my sharing the experience and board quality on this blog. Later when I assemble the new PCB to begin testing, I will share a few paragraphs covering PCBWAY. I took the opportunity to buy an SMD stencil, which should make my soldering much easier.

An SMD stencil is a thin piece of metal that has holes cut in it for every pad. Solder paste is spread across the stencil and is thus only deposited on the pads themselves on the board. My manual method of applying the paste left excess which turned to teeny solder balls that spattered around, while also being inconsistent enough that I couldn't guarantee a good connection of every pin. 

HOPED TO VERIFY THE SOLUTION WORKED BEFORE PRODUCING THE PCB

I wanted to breadboard some transistors to see if that would resolve the issues with spurious retriggering of the timer pulses. That was going to involve my bodging up another PCB blank, then using spare SLT ribbon cables to jumper this special board between my PCB and the 1130 system. I figured out a way to use the blank board to hold pins to form SLT sockets. 

I would be able to form two sockets, to handle eight sense output pins. One socket would connect to cable T4 from the 1130 and the other socket would plug into a jumper cable that is in turn plugged into my current PCB position T4. I would tack wires on pads connected to the pins and then run them to discrete transistors on a perf board. Signal quality wouldn't be great but I could validate the plan to work properly without the retriggering. 

Because the existing PCB has a NAND gate output, I would have to invert the signal with one transistor and then drive the open collector connection with a second. Thus the perf board would have 16 transistors and a bunch of resistors, all tenuously wired to the pads of the special PCB that acts as a pair of SLT connectors. 

However, a similar discrete PNP transistor with these low delay characteristics is obsolete, thus would cost several dollars per transistor and be tossed at the end of the test. The surface mount BSV52 transistors are way too tiny to try to tack on wires to the leads as it would be a very unreliable mess. 

I therefore had to gamble that this will work, ordering the BVS52 transistors and new PCB up front, then assemble it and only then see if the fix works. 

Checking out the low ESR cause for the 1130 MRAM ringing

QUICK VERIFICATION OF THIS THEORY OF A ROOT CAUSE

I soldered a  ohm resistor in series with the 4.7 uF ceramic capacitor. I then tried the board on the 1130 again and observed the operation. 

It failed in the same way as before. Perhaps the regulator itself is bad or I still don't have the Equivalent Series Resistance (ESR) in the stable range. 

I used a quick and dirty hack was to use an external 3.3V power supply after lifting the LD1117 from the circuit. I used heavy stranded wires between the supply and the board. This would let me know immediately if oscillation of the regulator is the root cause of my problems. 

And . . . it is not. The exact same failure mode occurred using a bench supply to power the logic. Arrgh. 

Time for a plan C. I will think on this a while and figure out something else to do that might resolve this problem. I think it is down to three possibilities:

1. The timer chips are either bizarre or defective, but that isn't likely since I see spurious repeats on the write timer chain as well as the read timer chain. 
2. Something in the 1130 side is causing this, some way that I am not understanding. 
3. Something on the PCB is causing this, maybe a combination of the decoupling capacitors and traces, again in a way I am not understanding.

That means my plan C has to be more of a desperation move where I change parts of the design just to see if a different set of parts or different approach avoids the problem. 

Oscillation in LD1117 voltage regulator appears to be the root cause

OUTPUT CAPACITOR ON REGULATOR IS CRITICAL TO STABILITY

This type of linear voltage regulator requires an external capacitor to achieve stability in its feedback loop, otherwise it can oscillate. The data sheet recommended a 4.7 uF ceramic capacitor of XR5 or XR7 dielectric type, which is what I used. 

Almost every power supply component is best with the lowest equivalent series resistance (ESR). However, I see reports that too low an ESR can lead to oscillation with this regulator. 

DATASHEET FOR THE REGULATOR IS NOT VERY HELPFUL

The data sheet recommended 4.7uF ceramic with XR5 or XR7, however those dielectrics are know for very low ESR. There is no discussion of having a high enough ESR, other than the charts buried near the end of the sheet. 

The data sheet shows how the regulator behaves with load variations but the chart provided has a rise time of 5 microseconds, much much slower than the rise time of the 80-100 ns pulses. Thus I don't know how this behaves with higher speed circuits driven by the regulator. 

Two charts show the stability region for the output capacitor, one for 5V output and the other for 1.2V output. My regulator is 3.3V, but I guess I can interpolate between the two charts since the manufacturer doesn't provide a specific datasheet for my part. It shows ESR at 100KHz frequency but my operating frequency is up over 10MHz. 

The bottom bound at 100 Khz seems to be an ESR of roughly.015 ohms so the next question is what ESR does my output capacitor exhibit at my actual operating frequency.

MY CHOSEN CAPACITOR HAS AN ESR THAT IS VERY LOW

The ESR is way, way below that level from approximately14KHz all the way up to roughly 70MHz. Thus any signal changes in that range risk oscillation of the regulator, exactly what I am seeing. Yikes. The smoking gun. 

SOME POSSIBLE FIXES FOR THE PROBLEM

I could choose a different voltage regulator part that doesn't have this issue, as long as it will drop in on the footprint of the existing PCB. I found a great part, Microchip Technology MIC39100-3.3 but its footprint is incompatible. It is SOT-223 just like the other one, but the middle pin and tab are ground on this one and output on the old part. It would require a new PCB version to work properly. 

The data sheet, however, tells me that a low ESR ceramic capacitor, like the one recommended for the old regulator, would also cause instability in this regulator. Instead, the recommend a tantalum of perhaps 10 uF as long as the ESR is 2 ohms or less. The datasheet was much, much more helpful than the prior regulator datasheet. 

Higher than 2 ohms, instability. Fractional ohms like my ceramic XR7 also unstable. However, the correct part, in the goldilocks zone of ESR, should work properly. 

I could source a 4.7uF or larger capacitor in the same 0805 footprint with a much higher ESR. In fact the same 10uF tantalum as for the MIC39100-3.3 should work properly on the existing LD1117 regulator chip.  

Avoiding changes to the PCB is desirable. First, it saves the delay waiting for a new board. Second, it avoids the labor of moving all the components over from one board to another. Third, it avoids all the connectivity testing I have to do verifying the SMD soldering. 

My first task is to do some testing to verify that it was the regulator oscillating, by adding a series resistor to the decoupling capacitor temporarily, or by removing the regulator chip and using a solid external power supply. Based on that, I can then try a higher ESR capacitor with the LD1117 and validate its good behavior. 

Same problem with 1130 MRAM in spite of new board

SCOPE SHOWS SPURIOUS RETRIGGERING DURING READS

The scope was set to trigger on the +STORAGE READ signal (yellow trace) activating. I displayed the sense output for the P1 parity bit (green trace) and P2 parity bit (purple trace), as well as the sense pulse for bit 15 (blue trace). Depending on the number of one bits in the stored data word - sense pulses are only generated when the bit value is 1 - I saw various amounts of retriggering occurring. 

The time chain produces a pulse about 800 nanoseconds after the +STORAGE READ rising edge. That is what gates sense output pulses when the bit value is 1. Retriggering means that the timing chain produces additional pulses 800 nanoseconds after the first one. Those force the Storage Buffer Register to have 1 bits in every position where sense output pulse arrives, but the retriggered pulses will corrupt the register during unrelated cycles, causing the processor to work incorrectly. 

My first display when I powered up was a word that had six bits of the word set to 1, thus generating six sense output pulses plus pulses on parity bits P1 and P2 for a total of eight. The scope showed me three retriggers, similar to the defective behavior I was seeing in the past.

Data value b0000111100000110 

I then stored a word of b0000000000000001 which has only one of the data bits with a 1 value. Parity bit P1 is a 1 because the left eight bits need to have an odd number of ones, while parity bit P2 is off because the right eight bits already have an odd number of ones. No retriggering occurred as you can see in the scope output below:

You can see that bit 15 (blue trace) has a pulse because the bit value is one, and the parity bits P1 and P2 are 1 and 0 respectively. No retriggering.

I then added a second bit so that the data word was b0000000000000011 producing sense pulses on bits 14 and 15. Both halves of the word have an even number of one bits, so both parity bits should be a one. That is what I observed, but now there is one retriggered pulse making the system misbehave.

We observe that the more sense pulses produced, the more spurious retriggering occurs. I moved the blue trace to the +3.3V rail of the PCB and watched it in AC mode so that I saw disturbances on the rail. The same case as above, the one with one retrigger, shows the same pattern on the 3.3V rail in the trace below:

The 3.3V line rings 1 to 1.5V peak to peak, with the peaks right at the time when the trigger and retrigger take place. I went back to the original case with six data bits of 1 and both parity bits at 1, but watched the 3.3V rail. 

Now there are four rings rather than two, which are associated with the three spurious retriggers. I did a major rework of the PCB to address the voltage and ground rails to eliminate this kind of behavior. A ground and a 3.3V layer plus large traces and multiple vias carrying current from the power layers to the chip connections. I used multiple large stranded wires for the ground connection to the 1130. Decoupling capacitors were placed on the bottom of the PCB to place them as close to the VCC/ground pins as possible. 

Each sense output pulse sinks about 8 ma of current from the 1130 system, thus the worst case of a word of all one bits would generate 18 pulses for a sink of 144 ma over a duration of about 100 nanoseconds. Each of the chips that produces the sense pulse handles four bits, thus that chip sinks 32ma of current from the 1130. 

The chip is an open drain NAND gate which should not involve the 3.3V rail at all in the current being sunk - that should flow through the transistor to ground and back to the 1130. Unless there is something obscure inside the circuitry of the NAND gate that causes parasitic power consumption from VCC when the open drain transistor is sinking power from the 1130, this doesn't seem like a likely cause. 

When I test the output pulses with a pullup resistor on the workbench, there is no bounce but when I hook the PCB to the IBM 1130, there is all the current flowing through the transistors. I don't see the rail ringing nor the retriggering on the workbench, only on the real machine, but that is probably because the current flowing on the workbench is much lower. 

I am focusing on investigating ringing caused by the design of the PCB and circuit. It is possible to have the decoupling capacitors on a board create ringing if they reach a resonance at the frequency of the sense pulses. This would happen if the inductance, resistance and capacitance of the capacitors and the traces have values that line up to create strong resonant peaks. 

If that is indeed what is happening, there are ways I can resolve this by changing component values or tweaking other aspects of the design. Since this is a new PCB version where I made very substantial changes to the traces, including rounding every change in direction to reduce reflections. the trace impedance values have to be pretty different, yet the ringing is the same. This suggest that it is the decoupling capacitors or the voltage regulator that is the root cause.

Beginning testing of new PCB for 1130 MRAM board

NEW PCB READY FOR TESTING

I had spent many hours checking continuity for all signals on the board and eliminating the chance of any shorts to adjacent pins. On the testbench I verified that all the outputs are producing correct pulses and the parity generation produces the proper pulses. The new PCB was installed on the 1130 system where I will do the final testing. 

MANUAL LOAD AND DISPLAY TESTS

Using the rotary mode switch, I could set it to LOAD and push the Prog Start button to load the pattern in the console entry switches (CES) into the memory location set by the Instruction Address Register (IAR). Turning the mode switch to DISPLAY and pushing the Prog Start button will read memory and display its output on the Storage Buffer Register (SBR) lights. 

To set the IAR to a particular address, I set the address in the IAR, set the mode switch to LOAD and push the Load IAR button on the console. This way I could put multiple patterns into memory.

Using this, I verified that I could set patterns which would be read back correctly. Changing the CES and storing different patterns first, I went back and displayed the locations to verify that what I stored was what was returned, including correct parity. 

I did not yet set up the oscilloscope to verify that I wasn't experiencing any spurious retriggering of the read or write timer outputs. That was the main issue I was experiencing with the prior PCB. Off visiting family for a few days and handling other obligations but will get to this soon.

FILLING STORAGE WITH A CHOSEN PATTERN

Turning the rotary mode switch to RUN restored normal function. I then opened the top cover to access the six customer engineer toggle switches. Turning on the Storage Load toggle switch set up the machine to loop through memory repeatedly storing the value set in the CES into all memory words. I pushed the Start button to begin the filling process and used the rotary mode switch to halt the operation by momentarily switching it away from RUN.

I then turned the rotary mode switch back to DISPLAY and checked some locations. The location is set in the CES, Load IAR is pushed, then Start is pushed to read back the stored value. 

Some patterns led to a parity check stop. If I am still seeing spurious read pulses updating the 1130 Storage Buffer Register at the wrong time, that might be causing this issue. Alternately I might have some issue on the board that I didn't catch on the test bench. Using the scope will help me understand what is happening. 

Worse as far as I am concerned, it appears that during these stops location 0 is overwritten with the contents that were being fetched from the address with the error. I will need to understand this failure mode and block it - that might require an update to the design. 

Replacing some chips on 1130MRAM board based on testing

TOGGLING STORAGE READ AND OBSERVING THE SENSE OUTPUTS

I have the board set up with a switch that will drive a rising edge on the +Storage Read line, causing my board to emit a sense pulse for any data or parity bit whose value is a 1. The output has a pullup resistor to +3.3V and a sense pulse consists of a short pulse to ground for less than 100 nanoseconds, occurring roughly 800 ns after the rising edge of the triggering signal. 

SUSPICIOUS RESULTS

When the memory chip was not yet installed, most sense bits appeared to be a 1 and produced pulses, but not bits 2, 3, 4, 13 and 14. The two parity bits produced pulses when odd parity existed on the eight bits they covered - those were correct based on which bits were generating pulses. 

SEVERAL CHIPS COULD BE THE CAUSE

I removed the buffer chips to see if they were holding down the five erroneous bit positions. This is a tri-state buffer that will drive the data line on the memory chip when we are doing a write, but floats to let the memory chip produce an output during all other times. With the chip removed, all the data bits appeared to be a 0, thus it was the tristate outputs of the buffer chip that were sensed as a 1. 

The data outputs feed into a NAND gate which produces the sense pulse when the data bit is 1 and the timer chain drives the output pulse at the correct time in a read. One more chip is connected to the data lines, an XOR chip that is used to calculate the odd parity and produce the parity bit value. 

Thus, the cause for bits 2, 3, 4, 13 and 14 to act differently could have been the NAND gate, the XOR gate, the buffer chip or the memory chip. The memory chip driving an output during a read, the other three chips having a bad input that pulls down the data line. 

REMOVING VARIOUS CHIPS TO NARROW DOWN THE CAUSE

I desoldered various chips to help identify which chips needed replacement. With the memory chip uninstalled but the others there, I observed the problems. When I yanked the buffer chip from one location, the problem bits from that side seemed to go away. When I soldered down the memory chip but had the two buffer chips removed, the results were still mixed. 

There were some differences from the prior condition, but not all bits acting the same either 1 or 0. That could be the contents of data in the chip that are driving those results, but it could also be the XOR chip inputs causing the problem or the NAND outputs.

I had changed the NAND chip that produced bits 12, 13, 14 and 15, but still had the same results in the earlier tests before the memory chip was installed. However, I could have an issue with the chips that output 2, 3, and 4 - two different chips as one handles 0-3 and the other covers 4-7. 

ORDERING REPLACEMENT CHIPS

I have spare NAND chips on hand, but no spares for the buffer nor the XOR chips. I placed orders with Digikey so that I can swap in known good chips in these positions and continue my testing until I am satisfied that the sense outputs are working properly on the test bench. Only then will I move over to the 1130 and test with this cabled into the system.