Output of Schmidt Trigger after a bit more massaging

Here is the turn-on and turn-off points I am achieving against the 3V SLT signals such as +Storage Read. These are very satisfactory.

As you can see, it won't switch to logic high until the SLT line rises over 2.3V and it won't flip down to logic low until the SLT input drops below 0.63V. This is an appropriately large sledgehammer to stomp on the signal noise. 

The output that I have to down-convert in order to drive a CMOS input is swinging up to 3.0V when the signal is on and dropping to a bit over 2V when the signal is off. 

I will simulate a circuit that produces a sharp 0 and 3.3V output corresponding to the 2+ and 3V levels above. Still tweaking that part of the circuit. 

Investigations for 1130 MRAM board - ways to block retriggering of the timer chip

DESIGNING WIDE SCHMIDT TRIGGER CIRCUIT

I see that the noise that shows up on the +Storage Read or +Storage Write line dips from 3V down to just under 2V, which is enough to overcome the Schmidt Triggers in the timer chip. It thus looks like a request to trigger anew. A Schmidt Trigger is a gate with asymmetric on and off voltage levels. It has an upper and a lower threshold voltage, where it switches on only when the input rises above the upper threshold. It won't switch off until the input drops below the lower threshold. 

The thresholds on chips are set for modern signaling levels, such as TTL or LVCMOS 3.3V.  SLT has its own signal levels which are not the same as the modern devices. While I can get away with using LVCMOS 3.3 devices with SLT in most cases, SLT defines logic low at .3V or less and a logic high at 1.8V or higher with full high at 3V. 

The signal causing the problems shoots up to 3V and stays there, but has some noise that dips down to just under 2V briefly. According to SLT, that is a valid high signal and it never went to low. The timer chip devices a logic high as 2V or higher and a logic low as .8V or lower. The dip in the noise is seen as a brief change to logic low and a return to logic high - viewed from the timer chip - but is not an issue for the 1130's SLT logic. 

Texas Instruments datasheet for the SN74LVC1G123 chip states that the inputs have 'sufficient hysteresis to handle slow input transition rates with jitter-free triggering of the outputs.' The intent here is that a very slow signal change may wobble around the turn-on threshold voltage and be seen as many on and off transitions. Their design aims to reduce that risk by having different upper and lower threshold voltages. 

They don't define the threshold voltages specifically but the datasheet recommends minimum logic high inputs of 2V and maximum logic low inputs of 0.8V to work reliably with a 3.3V VCC. The noise on the input dips below the 2V for a very brief time, but sufficient for the timer chip to retrigger because it thinks it went low. The voltage thresholds are not handling this situation. 

I began to whip up a wider range Schmidt Trigger for the inputs, one I would set to turn on when a signal hits 2.4V and to not turn off until it drops to 0.8V. That is a sufficient span to ignore the noise on the input lines. I did this with discrete transistors and the aid of LTSpice to simulate the circuit at full speed (about 277KHz) for the input memory signals. 

Complications abound. The SLT output that drives the +Storage Read and +Storage Write signal uses a germanium transistor with a 750 ohm pullup resistor to +3V. The transistor has only a 0.3V drop due to the properties of Germanium, which is why SLT uses 0.3 as a logic low threshold. Worse, the 750 ohm pullup must be factored into any circuit receiving the signal as the voltage detected on the transistor receiving the signal will be divided down by a resistor in the trigger circuit. 

Thus if I have a trigger circuit with a 100 ohm common emitter resistor, the input voltage seen at the base of the transistor is 100/850th of 3V, or only about .353V which is below the 0.6V diode junction of modern silicon based transistors. I have to bump up the common emitter resistor quite a bit to get a good voltage swing for the incoming signal. This drops the current through the transistors making them a bit slower to switch. 

I worked up a circuit with a common emitter resistor of 1.5K that switches on at 1.85V and switches off a 0.9V. This is not the ideal range I envisioned but enough to work properly with the noise I am experiencing on the input line. The circuit produces an output that swings between 2.4V and 3V which I then have to convert to voltages that will trigger the CMOS input circuitry inside the timer chip. 

I don't have the detailed circuit of the timer chip, but I can model a typical CMOS inverter input and simulate until my design works reliably with the conditions I am experiencing. I am working on that final piece right now. 

I have been doing quite a bit of simulation, experimenting with the characteristics of the flat ribbon cables used in the IBM 1130 to deliver the signal to my PCB. Using the characteristic inductance, capacitance and resistance, I modeled SLT driver and receiver gates and looked for any kind of reflections or noise on the line in different conditions. 

I then modeled with an SLT output gate, the cable, and a CMOS inverter input gate to see if there was bouncing, ringing or other phenomena that might explain my situation. To no avail so far. Ringing or bouncing should happen on the rise or the fall of a signal, not 1 microsecond into a 1.6 uS steady signal. This is asynchronous to what is going on in the IBM 1130 so I have a very hard time believing that it is the cause of this glitching. 

If I have to build the Schmidt Triggers for the two inputs, it will add about thirty small parts to the design and require another expensive round of PCB manufacture. I think I could breadboard the trigger circuit and insert it temporarily just to see if I can bypass the problems. This does feel like a Rube Goldberg fix to a problem. I will be much happier if I can figure out why this is happening and can fix it at the source. 

Continued testing of 1130 MRAM board - results of probed points and added power wires

TRACES OF KEY SIGNALS AFTER CHANGES TO BOARD

No change with added power lines to the chips. A dead end I believe.

FOUND SHORTED OUTPUT LEAD ON WRITE TIMER CHIP

The reason my write timer chain wasn't producing pulses was a consequence of my having tacked a wire onto the lead to observe it. Somehow the trace came a bit loose and the trace plus lead moved over to touch the adjacent pin, which on this chip is ground. 

I removed the chip with my hot air station then soldered it back down with solder paste and the heat gun. The write time now fires when +Storage Write has a rising edge.

RETRIGGERING HAPPENING ON BOTH READ AND WRITE TIMER CHAINS

The same issue arises on the write timer chain - as the first timer output pulse ends, thus triggering the second timer, there is noise on the +Storage Write trigger signal and the first timer repeats. The write timers are on the other side of the PCB from the read timers, yet have the same behavior. 

WATCHING SOURCE GATE IN 1130 ALONG WITH RETRIGGERING AT PCB

The source signal from the originating gate in the 1130, compartment B A1 card J2, has the same glitching as the +Storage Write signal onboard my PCB. These are the same as what happens on the +Storage Read signal and its timer chain. 

Purple is source gate, yellow is input to my timer chip

This did get me thinking. Every problem like this is an analog circuitry problem, masked by the digital abstraction of timer chips or NAND gates. The timer chip does not come with a schematic of the internal circuitry thus I can't model this exactly. What might be happening inside the timer chip, the cable and the 1130 gate that could do this?

SUSPICION OF BACKFEED OF VOLTAGE FROM TIMER CHIP THROUGH ITS INPUT

I am wondering if the SN74LVC1G123 timer chip is somehow backfeeding the +Storage Write (and +Storage Read) lines as it finishes its timed pulse. The SLT logic in the IBM 1130 uses +3V for logic high and that is what we see on the +Storage Write line when it is active. The chips on my board, however, are operating at 3.3V not 3V.

What if the shutoff of the pulse somehow delivers 3.3V back to the input pin, perhaps through a protective diode, which then rings based on the impedance of the cabling and the details of the source gate in the 1130? When my board is disconnected, the signal from the 1130 looks great. When my board is connected, there is ringing even back at the source. 

EXAMINING DETAILS OF SOURCE AND DESTINATION GATES IN 1130

I will look at the analog circuitry in the gate producing the +Storage Write (or +Storage Read) signal and at the gate in the IBM core memory compartment that normally would have received the signal. That will give me component values that I can plug into models in LTSpice where I can see if I can explain the ring or resonance based on capacitance, inductance and the resistances in those gates and the cabling between them. 

Sadly I don't have the schematic for the TI timer chip to model its input properly, but I can make some assumptions and see whether I can explain the waveforms I am seeing. 

Continued testing of 1130 MRAM board - more probes added to zoom in on problem area causing retriggering

ADDED EXTRA ENERGY PATHS TO VCC AND GROUND ON THE NAND CHIP

I added wires to the VCC and ground pins of the 74HC00 chip to lessen resistance to current flow that might be causing voltage drops that 'bounce' the ground or 3.3V power flows to the chip. I previously did this for the SN74LVC1G123 timer chips that are retriggering, but the worst behavior I am seeing is coming from the NAND gate that drives the timer. 

RETRIGGERING EXISTED BEFORE MY TRIGGERING MODIFICATIONS

Originally the design had the +Storage Read signal directly connected to the timer chip trigger (~CLR pin) but I realized that this was a design defect, so I began to AND this signal with the +Storage Use signal before triggering the timer chip. The problem was that +Storage Read will always occur even when the storage cycle should not use memory, instead gating data from peripheral devices for example. 

The timer will ALWAYS produce pulses to set the B register bits for any bit of the MRAM chip on my board that has a 1 value. The MRAM chip will always output the value in memory of the word addressed by the current SAR register address bits, thus if any are a 1 then they will flip on the B register during cycles when it shouldn't, like the peripheral I/O case I mentioned. 

The modification I made to solve the incorrect B register setting issue mentioned above was to use one of the four NAND gates on the 74HC00 chip, reroute signals like +Storage Use and +Storage Read, switch the timer chip to trigger on a falling edge by changing the ~A, B and ~CLR input values, and connecting the newly used gate to the different trigger pin of the timer. 

Due to existing traces to the pads of the 74HC00 and timer chip, I had to cut traces, lift up some chip leads off the pad of the board, and use bodge wires. This is messy and caused several rounds of resoldering of the chips that might have introduced solder joint issues. 

I see the worst of the signal anomaly on the output of the newly used NAND gate, but I was having the retriggering problems before all this so the root cause predates the modification. My modification may be more susceptible but isn't sufficient to explain it. 

SOLDER JOINTS HAVE BEEN A PROBLEM WITH THIS BOARD

Putting the very small surface mount parts on the board is a challenge, since a soldering iron tip is larger that the space between chip leads. It is very easy to have blobs form across multiple leads causing shorts, which I had to wick up with solder braid. The resulting cleaned off joint might appear to be a good connection but not actually have metal fused between the bottom of the lead and the pad on the board. 

In hindsight I should have used solder paste and a hot air gun to solder the tiniest chips to the board, achieving a good connection without the messiness and errors that crop up with traditional soldering. 

Continued testing 1130MRAM board - retrigger problem continues to bedevil me

STRONG FILTERING ON INPUT DID NOT STOP THE RETRIGGER

I upped the RC network to a much longer time constant to see if that would block a short duration glitch on the input. The image below shows the incoming +Storage Read signal in yellow and the output of my filter in green. Purple is the output of the NAND gate. Blue is an unrelated signal. 

The rising edge of the 1130 control signal is smoothed out and has a slow slope, so that the NAND gate doesn't trigger until about 450 nanoseconds after the actual signal rising edge arrived in yellow. However, the short duration noise in yellow would definitely be absorbed yet we see stronger noise after my filter. 

FOCUS NEEDS TO BE TOTALLY ON MY BOARD

I am convinced that the problems are not coming from the 1130 signal +Storage Read nor any issue such as lack of termination or induction on the cables. They are generated on my board. I will keep plugging away at this until I figure out the problem and resolve it. I believe the board will work well once I get this side issue fixed.

Retrigger of 1130MRAM likely due to slight wobble on trigger signal

POST ON TI SUPPORT FORUM COVERS A SIMILAR ISSUE

I found a post where another engineer was having issues with the SN74LVC1G123 chip retriggering spuriously. The situation is slightly different, where the retriggering happens just before the input signal goes low again whereas in mine it happens in mid pulse during a bit of noise. 

The data sheet claims that two of the inputs have Schmitt triggers, the clear input I am using does not,  and will only trigger when passing a voltage threshold. That threshold should be below 2V. The forum post does say that the engineer decided the very slight dip near the end of their input was the cause. This is far from the 2V level but apparently does fire off the timer spuriously. 

The fact that my NAND gate does show a pulse means it too found the input had changed enough to change the logic state. The gate combines +Storage Read and +Storage Use to produce the trigger, which I see go low but with a very short pulse to high right where the retriggering occurs. 

I am going to return to my RC lowpass filter with more aggressive values to see if I can block the dip on the NAND output even with all 1s on the data word. 

Side project - MV864A meter restoration - converting manual calibration/test instructions to the version I own

TEST POINTS HAVE CHANGED SIGNIFICANTLY BETWEEN VERSIONS

When Millivac re-engineered the meter from the germanium transistor technology design that I own to make use of more modern silicon semiconductors and more precise resistor values, they renumbered everything. There are fewer coupling transformers and more transistors in the new design that is reflected in the manual I purchased, in addition to every part having a different number. 

The manual's power supply test points 4TP1, 4TP2 and 4TP3 became TP62, ground and TP63 on my schematic. The manual's test points on the main board are:

• 3TP1
• 3TP2
• 3TP3
• 3TP4
• 3TP5
• 3TP6
• 3TP7
• 3TP8
• 3TP9
• 3TP10
• 3TP12
• 3TP13

My meter has test points:

• TP21
• TP22
• TP23
• TP24
• TP25
• TP26
• TP27
• TP28

The version in the manual has seven jumper wires soldered on the board, which can be disconnected to isolate the different sections for debugging.  On the schematic in the manual, there are wire 3W1, 3W2, 3W3, 3W4, 3W5, 3W6, and 3W7. On my board, there is a wire soldered across TP22 and TP23, plus points TP24 and TP28 have posts upon which wire could be soldered.

This is important as the testing recommendations jumper 3W3 is opened to check the modulator and preamplifiers. To check the main amplifier, jumper 3W4 is added between 3TP3 and 3TP13 while jumper 3W3 is relocated to bridge 3TP9 and 3TP10. 

On my meter, the equivalent of 3W3 is the wire soldered between TP22 and TP23, thus removing it would let me check the modulator and preamplifier sections. I don't see anything corresponding to how the jumper 3W4 would be used on my meter to test the main amplifier. 

WAVEFORM OBSERVATION POINTS

With the wire removed between TP22 and TP23, I should be able to adjust the zero control pot R257A to get a minimum amplitude waveform at TP22 with no signal applied to the meter. Inputting a 100 microvolt signal to the meter should produce a 400mV peak to peak 94Hz almost sine wave at TP22.

It is less clear how to monitor the output of the reference amplifier since the circuit is so different but my guess is that I should monitor at TP28 where I should see a 46V peak to peak 94Hz signal with the 100 microvolt input to the meter. The method of adding jumper 3W4 and moving 3W3 is used to adjust the gain potentiometer, but I don't see at this time how I could achieve a similar test that would produce meter needle sitting between 45 and 55% of full scale. 

Checking the driver circuit should involve looking at TP24 where I would see a very low signal at 3V peak to peak with a zero input to the meter and a 94Hz rectified signal at 5V peak to peak when there is a 100 microvolt input to the meter. However the circuit is different enough that I won't immediately consider that I have a fault if the waveform doesn't match the manual. 

POWER RAIL RELABELING

The power supply in the manual has test points 4TP1, 4TP2 and 4TP3, while the boards on my meter have points TP62, TP63 and Ground. The manual labels those points as -6V, +8.5V and ground, whereas my test points register -14.5V and -6V against ground. The testing section of the manual tells me to measure between 4TP2 and 4TP1 adjusting a pot to set the voltage to -14.5 but on my meter I see -14.5V between TP63 and ground. 

The version in the manual seems to have reversed where the ground sits, in other words swapping the meaning of ground between 4TP2 and 4TP3. That makes it even harder to reconcile the schematics between the two, since the manual would show transistors with connections to +8.5V while on mine the same transistor would be connected to ground. 

CALIBRATION REMAINS THE SAME FORTUNATELY

The process of calibration involves applying reference voltages, currents and resistances while adjusting small pots on the rear of the meter to get the meter reading to match. There are multiple ranges for the meter each of which has its own adjustment pot for voltage ranges. Current ranges have multiple pots but several ranges are combined into one pot. 

Voltage adjustments are made at 100 microvolt, 300 microvolt, 1 millivolt, 3 mV, 10mV, 30mV, 100mV, 300mV, 1V, 3V 10V, 30V, 100V, 300V, and 1KV inputs. Current adjustments are made at .1 microamp, .3 microamp, 1 microamp, 3 microamp, 10 milliamp, 30mA, 100mA, 300mA, 1A and one adjustment for all ranges between 10 microamp and 3 mA. Resistance checks are made by setting the full scale ohms pot to infinity before each range measurement, but for the two lowest resistances one must first short the inputs and adjust the zero meter pot then set the full scale infinity pot before the measurement. 

A final linearity check is done on the 1V range while adjusting the input to the meter to 100mV, 200mV, 300mV, 400mV, 500mV, 600mV, 700mV, 800mV, 900mV and 1V while validating the needle position on the meter.