PREPARED TO RUN THE DIAGNOSTIC BUT IT HALTED WITH PARITY ERRORS
I used the memory loader to place the 309 diagnostic into memory and then started it running at location 249 so that I could hit interrupt request to cause the diagnostic to begin running. I found the machine stopped with a parity error.
The data from memory (Storage Buffer Register) had four bits turned on in the left halfword, which would require the P1 parity bit to be turned on to achieve odd parity. Since it wasn't on, the system stopped with a Parity check. The right halfword has one bit on and the P2 bit is correctly at 0 to result in odd parity for that side.
Some parts of the display are difficult to read, an artifact of the scan rate of my phone camera and the display lamp operation. The Instruction Address Register is 0389 and the Storage Address Register is 0388. This is fetching an instruction (I1 instruction phase) which appears to have been a BSC I instruction with an offset of 0010. We don't know the second word of the instruction because we stopped on the fetch of the first instruction word (I1).
I tried resetting the machine and running, but got three more Parity Check stops after each attempt.
There is not enough visible on the first of the three stops above other than it failed while reading the operand of an instruction (E1 instruction phase) from location 0201 where it appears it received a word of 0000 but the two parity bits P1 and P2 were not set. I suspect this was an artifact of stopping and resetting the system after the prior Parity Stop.
The second of the three stops above has IAR of 028D meaning we are executing the instruction from 028B and 028C. The instruction was interpreted as a 68xx which is a register update instruction, picking up a value from 0015 which has a parity error in the left half.
The last of the three stops above has IAR of 0005 with an SAR of 0005 and the SBR left halfword with three bits on does not have the requisite P1 bit set.
A common feature of three of the four is bit 3 being set with a parity error in that halfword. I checked this by doing a Storage Load function on the console setting 0000 to all locations in memory. When I ran the Storage Display function we stopped with bit 3 on and a parity error.
BIT 3 IS WRITTEN AS A 1 EVEN WHEN 0 IS INTENDED - INHIBIT FAILURE
I stuck a voltmeter on the inhibit input to memory for bit 3, turning the machine to Load mode where the input to memory will be the console entry switches on the front of the machine. As I flipped switch 3 up and down, the voltage flipped between 3V and nearly ground, indicative of proper input from the 1130 to the memory gate.
This is almost certainly an inhibit failure for bit 3. When the memory does a write cycle, the X and Y lines try to flip the addressed core to the 1 direction. If a reverse current flows through the inhibit/sense wires, the core will not flip to 1; if no inhibit current, then we set it to 1. Regardless of the logic level that is input to the inhibit, the core flips.
l tried various addresses and confirmed that bit 3 will ALWAYS be written to 1 for addresses from 0 to 4097, but the bit works properly for addresses in the second 4K of memory. This localizes the error to the low 4K circuitry.
CHECKING RESISTANCES ON THE STACK MAY SHOW OPEN GROUND CONNECTION
I did a quick ohmmeter check on the pins going to the sense/inhibit wires for bit 3 in the low 4K and saw indications that the ground connection might be an open circuit. To make a more definitive test I have to pull the sense/inhibit driver cards before I test the wire resistance. However, this is a type of failure we have seen before.
MULTIPLE FAILURES HAVE OCCURRED ON THE SAME PCB BOARD IN THE STACK
The core memory stack that is mounted in the center of the memory logic gate has printed circuit boards at the bottom and top of the sandwich, as well as eighteen core memory planes in the middle. The top PCB holds the steering diodes that allow a reasonable number of drivers to connect to any of 4098 cores in a plane for a 4K segment. The bottom PCB routes signals from the edges of the PCB to pins arrayed across the bottom area.
Wires from the core planes run down to be soldered onto the edge of the bottom PCB. These signals follow traces to pins that stick down out of the bottom PCB. These pins fit through holes drilled in the glass backplane. On the rear of the backplane, connectors bridge the pins from the memory stack to pins attached to the backplane. This is how circuitry on the backplane is connected to the core stack, with logic cards arranged around the sides of the backplane.
The trace is not visible from the bottom of the core stack, as they sit on the surface under a core plane. Thus I have no way to look inside nor to make repairs. Trying to take the sandwich of layers apart would involve unwelding many connections to all those core planes.
I have run jumper wires to bridge open circuits that were discovered when other parity problems arose in the past during the restoration of this system. There is no sign of a crack on the PCB and no commonality in the areas where the pins for the failed circuits are mounted. I suspect some kind of erosion or contamination, perhaps mouse urine from the extensive infestation this machine suffered in past decades.
MY FEAR IS THAT THE SYSTEM WILL EXHIBIT ADDITIONAL FAILURES OVER TIME
If this is yet another failed connection, I might be able to jumper it but the reality is that if we have encounted progressive failures to date, it is likely those would continue. There are a total of 108 connections for sense/inhibit lines across the 8K core stack.
Until I finish careful debugging of this new parity issue, I can't be certain that it is a new break in the lower PCB of the stack. If it is, that will be disturbing.
INVESTIGATING AN ALTERNATE 8K WORD MEMORY FOR THE SYSTEM
The interface between the rest of the IBM 1130 and the core memory gate is pretty simple. The memory, with a read-then-write that takes place over a glacial 3.6 microseconds, will be very easy to replace with a substitute.
It should be non-volatile, just as core memory is, thus I am investigating devices such as MRAM chips that have plenty of speed, capacity, infinite lifetime of reads/writes and decades long non-volatility.