1130MRAM spurious retrigger - what it can not be then musings

NOT A FAULT OF THE CONTROL SIGNALS

The control signals that fire off the timer chips are +Storage Read and +Storage Write. They are produced by the IBM 1130 using the circuitry below:

Four flipflop outputs T0, T1, T2 and T3 are wired together in a dot-OR configuration, where a pullup resistor (750 ohms to 3V) will produce a high output if none of the four feeding gates are conducting but any one or more of them turning on will pull the shared line down to ground. Thus this is high if none of T0, T2, T2 or T3 are true. 

The 1130 storage cycle consists of eight clock steps T0 through T7, with the first four used to destructively read out the sense bits of a core storage word and the last four used to write back the same or modified value into the word. 

This circuit feeds +Storage Write with the dot-OR output, so that we are in the write back portion of the cycle when we are NOT in T0, T1, T2 or T3. The output of the dot-OR gate also feeds through an SLT inverter to produce +Storage Read which is high whenever the dot-OR is low because it is T0, T1, T2 or T3. 

These output signals have a pullup resistor to make them sit up at +3V unless the transistor is conducting. Any of the dot-OR transistors conducting will thus result in 0V. If the dot-OR is high then the inverter gate transistor is conducting and +Storage Read is low; if any transistor in the dot-OR is low then the inverter gate transistor is turned off and +Storage Read is pulled high.

I put the scope on these signals with my board disconnected from the cables. All the wiring up to the cable connector was connected. The scope showed clean signals that went up and stayed flat at 3V for four clock steps, either T0-T3 or T4-T7. No noise, no glitch. 

GLITCH IS HAPPENING ON MY BOARD WHEN IT IS CONNECTED TO THE 1130

The noise shows up just as the first timer chip in a chain goes low, triggering the second timer chip in the chain to go high. The control signal (e.g. +Storage Read) then has the noise showing on its scope probe during that period of time, causing the control signal level to dip down below 2V which is seen by the first timer chip as a new trigger event. 

POSSIBILITIES FOR WHAT THE CAUSE MIGHT BE

Each of the sense output signals that will turn on the B register with the contents of a memory word are emitted during the high pulse of the second timer chip in the read chain. I believe this is about 8ma of current pulled for each output bit which is has a 1 value. Maximally I could be producing a word with all sixteen data bits at 1, which also requires the two parity bits to be 1, so 18 times 8ma or 144ma of current is being sunk over the cable from the IBM 1130 B registers. We have seen the retriggering is worse with higher number of 1 bits in the data word being returned.

This 80-100 nanosecond period of 144ma current flow might be inducing voltage on the control wires, although the sense bit signals are on cables T1 and T4 but the control signals are on the separate cable T3. More likely we have some kind of ground bounce between my PCB and the ground of the 1130 logic gates.

I have connected my board with a 16 gauge wire to the same ground terminal block that serves the logic compartments such as the one generating the control signals. If the 1130 itself is not suffering from detectable ground bounce, my board should be locked to it just as strongly. One layer of the PCB is ground, thus a very good path. However, we might still be getting some kind of bounce or resonance here that injects the noise into the control signals. 

I have a very beefy capacitor as a PCB buffer for the 3.3V power rail, plus wide traces for VCC, but the combined draw of the sense bits in that short time period might be pulling down VCC temporarily. I didn't see any signs of this nor of ground bounce when I used the scope on the VCC and ground pins of a timer chip. 

This may be some phenomenon of the particular timer chips when used in a chain - i.e. when the output of one ends as the trigger of the second. All the documentation for the chips covers them in single roles. 

Output of Schmidt Trigger after a bit more massaging

Here is the turn-on and turn-off points I am achieving against the 3V SLT signals such as +Storage Read. These are very satisfactory.

As you can see, it won't switch to logic high until the SLT line rises over 2.3V and it won't flip down to logic low until the SLT input drops below 0.63V. This is an appropriately large sledgehammer to stomp on the signal noise. 

The output that I have to down-convert in order to drive a CMOS input is swinging up to 3.0V when the signal is on and dropping to a bit over 2V when the signal is off. 

I will simulate a circuit that produces a sharp 0 and 3.3V output corresponding to the 2+ and 3V levels above. Still tweaking that part of the circuit. 

Investigations for 1130 MRAM board - ways to block retriggering of the timer chip

DESIGNING WIDE SCHMIDT TRIGGER CIRCUIT

I see that the noise that shows up on the +Storage Read or +Storage Write line dips from 3V down to just under 2V, which is enough to overcome the Schmidt Triggers in the timer chip. It thus looks like a request to trigger anew. A Schmidt Trigger is a gate with asymmetric on and off voltage levels. It has an upper and a lower threshold voltage, where it switches on only when the input rises above the upper threshold. It won't switch off until the input drops below the lower threshold. 

The thresholds on chips are set for modern signaling levels, such as TTL or LVCMOS 3.3V.  SLT has its own signal levels which are not the same as the modern devices. While I can get away with using LVCMOS 3.3 devices with SLT in most cases, SLT defines logic low at .3V or less and a logic high at 1.8V or higher with full high at 3V. 

The signal causing the problems shoots up to 3V and stays there, but has some noise that dips down to just under 2V briefly. According to SLT, that is a valid high signal and it never went to low. The timer chip devices a logic high as 2V or higher and a logic low as .8V or lower. The dip in the noise is seen as a brief change to logic low and a return to logic high - viewed from the timer chip - but is not an issue for the 1130's SLT logic. 

Texas Instruments datasheet for the SN74LVC1G123 chip states that the inputs have 'sufficient hysteresis to handle slow input transition rates with jitter-free triggering of the outputs.' The intent here is that a very slow signal change may wobble around the turn-on threshold voltage and be seen as many on and off transitions. Their design aims to reduce that risk by having different upper and lower threshold voltages. 

They don't define the threshold voltages specifically but the datasheet recommends minimum logic high inputs of 2V and maximum logic low inputs of 0.8V to work reliably with a 3.3V VCC. The noise on the input dips below the 2V for a very brief time, but sufficient for the timer chip to retrigger because it thinks it went low. The voltage thresholds are not handling this situation. 

I began to whip up a wider range Schmidt Trigger for the inputs, one I would set to turn on when a signal hits 2.4V and to not turn off until it drops to 0.8V. That is a sufficient span to ignore the noise on the input lines. I did this with discrete transistors and the aid of LTSpice to simulate the circuit at full speed (about 277KHz) for the input memory signals. 

Complications abound. The SLT output that drives the +Storage Read and +Storage Write signal uses a germanium transistor with a 750 ohm pullup resistor to +3V. The transistor has only a 0.3V drop due to the properties of Germanium, which is why SLT uses 0.3 as a logic low threshold. Worse, the 750 ohm pullup must be factored into any circuit receiving the signal as the voltage detected on the transistor receiving the signal will be divided down by a resistor in the trigger circuit. 

Thus if I have a trigger circuit with a 100 ohm common emitter resistor, the input voltage seen at the base of the transistor is 100/850th of 3V, or only about .353V which is below the 0.6V diode junction of modern silicon based transistors. I have to bump up the common emitter resistor quite a bit to get a good voltage swing for the incoming signal. This drops the current through the transistors making them a bit slower to switch. 

I worked up a circuit with a common emitter resistor of 1.5K that switches on at 1.85V and switches off a 0.9V. This is not the ideal range I envisioned but enough to work properly with the noise I am experiencing on the input line. The circuit produces an output that swings between 2.4V and 3V which I then have to convert to voltages that will trigger the CMOS input circuitry inside the timer chip. 

I don't have the detailed circuit of the timer chip, but I can model a typical CMOS inverter input and simulate until my design works reliably with the conditions I am experiencing. I am working on that final piece right now. 

I have been doing quite a bit of simulation, experimenting with the characteristics of the flat ribbon cables used in the IBM 1130 to deliver the signal to my PCB. Using the characteristic inductance, capacitance and resistance, I modeled SLT driver and receiver gates and looked for any kind of reflections or noise on the line in different conditions. 

I then modeled with an SLT output gate, the cable, and a CMOS inverter input gate to see if there was bouncing, ringing or other phenomena that might explain my situation. To no avail so far. Ringing or bouncing should happen on the rise or the fall of a signal, not 1 microsecond into a 1.6 uS steady signal. This is asynchronous to what is going on in the IBM 1130 so I have a very hard time believing that it is the cause of this glitching. 

If I have to build the Schmidt Triggers for the two inputs, it will add about thirty small parts to the design and require another expensive round of PCB manufacture. I think I could breadboard the trigger circuit and insert it temporarily just to see if I can bypass the problems. This does feel like a Rube Goldberg fix to a problem. I will be much happier if I can figure out why this is happening and can fix it at the source. 

Continued testing of 1130 MRAM board - results of probed points and added power wires

TRACES OF KEY SIGNALS AFTER CHANGES TO BOARD

No change with added power lines to the chips. A dead end I believe.

FOUND SHORTED OUTPUT LEAD ON WRITE TIMER CHIP

The reason my write timer chain wasn't producing pulses was a consequence of my having tacked a wire onto the lead to observe it. Somehow the trace came a bit loose and the trace plus lead moved over to touch the adjacent pin, which on this chip is ground. 

I removed the chip with my hot air station then soldered it back down with solder paste and the heat gun. The write time now fires when +Storage Write has a rising edge.

RETRIGGERING HAPPENING ON BOTH READ AND WRITE TIMER CHAINS

The same issue arises on the write timer chain - as the first timer output pulse ends, thus triggering the second timer, there is noise on the +Storage Write trigger signal and the first timer repeats. The write timers are on the other side of the PCB from the read timers, yet have the same behavior. 

WATCHING SOURCE GATE IN 1130 ALONG WITH RETRIGGERING AT PCB

The source signal from the originating gate in the 1130, compartment B A1 card J2, has the same glitching as the +Storage Write signal onboard my PCB. These are the same as what happens on the +Storage Read signal and its timer chain. 

Purple is source gate, yellow is input to my timer chip

This did get me thinking. Every problem like this is an analog circuitry problem, masked by the digital abstraction of timer chips or NAND gates. The timer chip does not come with a schematic of the internal circuitry thus I can't model this exactly. What might be happening inside the timer chip, the cable and the 1130 gate that could do this?

SUSPICION OF BACKFEED OF VOLTAGE FROM TIMER CHIP THROUGH ITS INPUT

I am wondering if the SN74LVC1G123 timer chip is somehow backfeeding the +Storage Write (and +Storage Read) lines as it finishes its timed pulse. The SLT logic in the IBM 1130 uses +3V for logic high and that is what we see on the +Storage Write line when it is active. The chips on my board, however, are operating at 3.3V not 3V.

What if the shutoff of the pulse somehow delivers 3.3V back to the input pin, perhaps through a protective diode, which then rings based on the impedance of the cabling and the details of the source gate in the 1130? When my board is disconnected, the signal from the 1130 looks great. When my board is connected, there is ringing even back at the source. 

EXAMINING DETAILS OF SOURCE AND DESTINATION GATES IN 1130

I will look at the analog circuitry in the gate producing the +Storage Write (or +Storage Read) signal and at the gate in the IBM core memory compartment that normally would have received the signal. That will give me component values that I can plug into models in LTSpice where I can see if I can explain the ring or resonance based on capacitance, inductance and the resistances in those gates and the cabling between them. 

Sadly I don't have the schematic for the TI timer chip to model its input properly, but I can make some assumptions and see whether I can explain the waveforms I am seeing. 

Continued testing of 1130 MRAM board - more probes added to zoom in on problem area causing retriggering

ADDED EXTRA ENERGY PATHS TO VCC AND GROUND ON THE NAND CHIP

I added wires to the VCC and ground pins of the 74HC00 chip to lessen resistance to current flow that might be causing voltage drops that 'bounce' the ground or 3.3V power flows to the chip. I previously did this for the SN74LVC1G123 timer chips that are retriggering, but the worst behavior I am seeing is coming from the NAND gate that drives the timer. 

RETRIGGERING EXISTED BEFORE MY TRIGGERING MODIFICATIONS

Originally the design had the +Storage Read signal directly connected to the timer chip trigger (~CLR pin) but I realized that this was a design defect, so I began to AND this signal with the +Storage Use signal before triggering the timer chip. The problem was that +Storage Read will always occur even when the storage cycle should not use memory, instead gating data from peripheral devices for example. 

The timer will ALWAYS produce pulses to set the B register bits for any bit of the MRAM chip on my board that has a 1 value. The MRAM chip will always output the value in memory of the word addressed by the current SAR register address bits, thus if any are a 1 then they will flip on the B register during cycles when it shouldn't, like the peripheral I/O case I mentioned. 

The modification I made to solve the incorrect B register setting issue mentioned above was to use one of the four NAND gates on the 74HC00 chip, reroute signals like +Storage Use and +Storage Read, switch the timer chip to trigger on a falling edge by changing the ~A, B and ~CLR input values, and connecting the newly used gate to the different trigger pin of the timer. 

Due to existing traces to the pads of the 74HC00 and timer chip, I had to cut traces, lift up some chip leads off the pad of the board, and use bodge wires. This is messy and caused several rounds of resoldering of the chips that might have introduced solder joint issues. 

I see the worst of the signal anomaly on the output of the newly used NAND gate, but I was having the retriggering problems before all this so the root cause predates the modification. My modification may be more susceptible but isn't sufficient to explain it. 

SOLDER JOINTS HAVE BEEN A PROBLEM WITH THIS BOARD

Putting the very small surface mount parts on the board is a challenge, since a soldering iron tip is larger that the space between chip leads. It is very easy to have blobs form across multiple leads causing shorts, which I had to wick up with solder braid. The resulting cleaned off joint might appear to be a good connection but not actually have metal fused between the bottom of the lead and the pad on the board. 

In hindsight I should have used solder paste and a hot air gun to solder the tiniest chips to the board, achieving a good connection without the messiness and errors that crop up with traditional soldering. 

Continued testing 1130MRAM board - retrigger problem continues to bedevil me

STRONG FILTERING ON INPUT DID NOT STOP THE RETRIGGER

I upped the RC network to a much longer time constant to see if that would block a short duration glitch on the input. The image below shows the incoming +Storage Read signal in yellow and the output of my filter in green. Purple is the output of the NAND gate. Blue is an unrelated signal. 

The rising edge of the 1130 control signal is smoothed out and has a slow slope, so that the NAND gate doesn't trigger until about 450 nanoseconds after the actual signal rising edge arrived in yellow. However, the short duration noise in yellow would definitely be absorbed yet we see stronger noise after my filter. 

FOCUS NEEDS TO BE TOTALLY ON MY BOARD

I am convinced that the problems are not coming from the 1130 signal +Storage Read nor any issue such as lack of termination or induction on the cables. They are generated on my board. I will keep plugging away at this until I figure out the problem and resolve it. I believe the board will work well once I get this side issue fixed.

Retrigger of 1130MRAM likely due to slight wobble on trigger signal

POST ON TI SUPPORT FORUM COVERS A SIMILAR ISSUE

I found a post where another engineer was having issues with the SN74LVC1G123 chip retriggering spuriously. The situation is slightly different, where the retriggering happens just before the input signal goes low again whereas in mine it happens in mid pulse during a bit of noise. 

The data sheet claims that two of the inputs have Schmitt triggers, the clear input I am using does not,  and will only trigger when passing a voltage threshold. That threshold should be below 2V. The forum post does say that the engineer decided the very slight dip near the end of their input was the cause. This is far from the 2V level but apparently does fire off the timer spuriously. 

The fact that my NAND gate does show a pulse means it too found the input had changed enough to change the logic state. The gate combines +Storage Read and +Storage Use to produce the trigger, which I see go low but with a very short pulse to high right where the retriggering occurs. 

I am going to return to my RC lowpass filter with more aggressive values to see if I can block the dip on the NAND output even with all 1s on the data word. 

Side project - MV864A meter restoration - converting manual calibration/test instructions to the version I own

TEST POINTS HAVE CHANGED SIGNIFICANTLY BETWEEN VERSIONS

When Millivac re-engineered the meter from the germanium transistor technology design that I own to make use of more modern silicon semiconductors and more precise resistor values, they renumbered everything. There are fewer coupling transformers and more transistors in the new design that is reflected in the manual I purchased, in addition to every part having a different number. 

The manual's power supply test points 4TP1, 4TP2 and 4TP3 became TP62, ground and TP63 on my schematic. The manual's test points on the main board are:

• 3TP1
• 3TP2
• 3TP3
• 3TP4
• 3TP5
• 3TP6
• 3TP7
• 3TP8
• 3TP9
• 3TP10
• 3TP12
• 3TP13

My meter has test points:

• TP21
• TP22
• TP23
• TP24
• TP25
• TP26
• TP27
• TP28

The version in the manual has seven jumper wires soldered on the board, which can be disconnected to isolate the different sections for debugging.  On the schematic in the manual, there are wire 3W1, 3W2, 3W3, 3W4, 3W5, 3W6, and 3W7. On my board, there is a wire soldered across TP22 and TP23, plus points TP24 and TP28 have posts upon which wire could be soldered.

This is important as the testing recommendations jumper 3W3 is opened to check the modulator and preamplifiers. To check the main amplifier, jumper 3W4 is added between 3TP3 and 3TP13 while jumper 3W3 is relocated to bridge 3TP9 and 3TP10. 

On my meter, the equivalent of 3W3 is the wire soldered between TP22 and TP23, thus removing it would let me check the modulator and preamplifier sections. I don't see anything corresponding to how the jumper 3W4 would be used on my meter to test the main amplifier. 

WAVEFORM OBSERVATION POINTS

With the wire removed between TP22 and TP23, I should be able to adjust the zero control pot R257A to get a minimum amplitude waveform at TP22 with no signal applied to the meter. Inputting a 100 microvolt signal to the meter should produce a 400mV peak to peak 94Hz almost sine wave at TP22.

It is less clear how to monitor the output of the reference amplifier since the circuit is so different but my guess is that I should monitor at TP28 where I should see a 46V peak to peak 94Hz signal with the 100 microvolt input to the meter. The method of adding jumper 3W4 and moving 3W3 is used to adjust the gain potentiometer, but I don't see at this time how I could achieve a similar test that would produce meter needle sitting between 45 and 55% of full scale. 

Checking the driver circuit should involve looking at TP24 where I would see a very low signal at 3V peak to peak with a zero input to the meter and a 94Hz rectified signal at 5V peak to peak when there is a 100 microvolt input to the meter. However the circuit is different enough that I won't immediately consider that I have a fault if the waveform doesn't match the manual. 

POWER RAIL RELABELING

The power supply in the manual has test points 4TP1, 4TP2 and 4TP3, while the boards on my meter have points TP62, TP63 and Ground. The manual labels those points as -6V, +8.5V and ground, whereas my test points register -14.5V and -6V against ground. The testing section of the manual tells me to measure between 4TP2 and 4TP1 adjusting a pot to set the voltage to -14.5 but on my meter I see -14.5V between TP63 and ground. 

The version in the manual seems to have reversed where the ground sits, in other words swapping the meaning of ground between 4TP2 and 4TP3. That makes it even harder to reconcile the schematics between the two, since the manual would show transistors with connections to +8.5V while on mine the same transistor would be connected to ground. 

CALIBRATION REMAINS THE SAME FORTUNATELY

The process of calibration involves applying reference voltages, currents and resistances while adjusting small pots on the rear of the meter to get the meter reading to match. There are multiple ranges for the meter each of which has its own adjustment pot for voltage ranges. Current ranges have multiple pots but several ranges are combined into one pot. 

Voltage adjustments are made at 100 microvolt, 300 microvolt, 1 millivolt, 3 mV, 10mV, 30mV, 100mV, 300mV, 1V, 3V 10V, 30V, 100V, 300V, and 1KV inputs. Current adjustments are made at .1 microamp, .3 microamp, 1 microamp, 3 microamp, 10 milliamp, 30mA, 100mA, 300mA, 1A and one adjustment for all ranges between 10 microamp and 3 mA. Resistance checks are made by setting the full scale ohms pot to infinity before each range measurement, but for the two lowest resistances one must first short the inputs and adjust the zero meter pot then set the full scale infinity pot before the measurement. 

A final linearity check is done on the 1V range while adjusting the input to the meter to 100mV, 200mV, 300mV, 400mV, 500mV, 600mV, 700mV, 800mV, 900mV and 1V while validating the needle position on the meter. 

Continued testing 1130MRAM board - retrigger redux

BOLSTERED GROUND CONNECTION OF THE TIMER CHIP

I added wires to increase the current capacity of the ground near the timer chip. I also bypassed the MOSFET that was included to isolate the board ground from the IBM 1130 until the +12V supply rail is present - to block backflow of current through gate inputs on my chips. 

ADJUSTED RC NETWORK SMOOTHING

I doubled the time constant of the RC network that should slow the edges of the pulses and absorb any very short glitches. I did this for the +Storage Read and +Storage Write signals that are what trigger the timers and could be the cause of the spurious retriggering. 

When I look at the effect of the smoothing filter, it cleans up the edges of the signal a bit and slows the rise but the noise in the center is unchanged, because I don't think it is coming in on the input but is instead being induced by something on my board.

WATCHED SIGNAL PATH FOR +STORAGE READ SIGNAL

I put one scope probe on the originating gate of +Storage Read in B-A1 slot J2 pin B13, another on B B1 slot E1 pin E11 where the cable enters compartment B1 after it leaves the source at compartment A1. It exits the compartment on B B1 H1 pin E11 and comes over cable T3 to my board where I hung a third scope probe at the signal as it entered the RC network on my board. The fourth probe was placed on the output of a NAND gate which combines +Storage Read and +Storage Use signals to produce a low output whose falling edge triggers the time. 

The waveforms were quite clean all the way through until the NAND gate. It is there that I see the sharp pulse right at the time of the retrigger. One theory is that something is wrong with the NAND gate causing the pulse. The two inputs stay high through the point of instability.

The yellow signal is +Storage Read and the green signal is the output of the NAND gate. At the bottom in blue is the pulse produced by the second read timer. Notice the sharp peak from the NAND, coming all the way up to 3.3V from 0 for perhaps 10 nanoseconds. 

 

WATCHING THE RETRIGGERING POINT ON THE SCOPE

The next experiment I did was to watch the relative timing between the different signals. Yellow monitored the VCC pin of the first read timer chip. Green is the bump in the NAND gate output when we have the retrigger. Purple is the ground pin of the first read timer chip and blue is the output of the second read timer chip. 

The impact on the NAND gate signal happens after the pulse rises from the second read timer chip. This suggests that the pulse is an early event in the chain leading to the retrigger. I then changed the scope probes slightly and watched again.

Blue is still the output pulse of the second read timer, while purple is the output of the first read timer chip. Its long 800ns pulse is ending which becomes the trigger for the second read timer chip. The green line is the pulse on the NAND gate. Relative timing is that the second chip pulse fires, whatever occurs drives the NAND output up and the retrigger happens about the same time. This is still not definitive for causality. 

DIGGING INTO POWER DELIVERY TO THE TIMER AND NAND CHIPS

I then moved on to the possibility that it is still an issue with the energy delivery rate from the 3.3V rail to the chips displaying problems. I had mentioned in earlier posts that when the word being read out has many bits on, the retriggering issue is noticeably worse than when reading a word of all zero bits. Each one bit being delivered sinks about 8ma of current from the IBM 1130 -Sense Bit x connections. 

I used an entire layer of the board as a ground plane, plus widened the 3.3V rail traces significantly. I believed this was over-engineering and rendered the PCB relatively safe from power rail sagging during gate switching. I decided to look closer to see whether there is any weakness that I hadn't considered, and I think I found it!

The yellow rectangles show the locations of the NAND chip and the two read timer chips. On the left side of the PCB you can see the wide traces for 3.3V delivery in red, but then the 3.3V wide trace is down on the bottom layer of the PCB. It may be wide, but look at where the power transitions from the top layer (red) to the bottom layer (blue). A single via with 15 mil diameter is what carries the power across the layers. 

That should support over one ampere if the via heats up 10 degrees over ambient, with just a few millivolts of voltage drop. Indeed my probes on the VCC pin of the timer chip shows that the 3.3 rail is pretty constant and does NOT dip down any appreciable amount. The decoupling capacitors for each chip will provide short term energy to the chip. 

Previously I had also watched the VCC and ground pins of the read timer chip without seeing much wiggle of the trace. I didn't watch the NAND gate however the retriggering problem existed before I began routing the +Storage Read signal through the NAND gate, thus I have to believe the spike I see on the NAND output is flowing back from the timer chip and not a deficiency in the gate itself. 

I will add some wires to the ground and VCC pins of the two read timer chips to bypass any chance that the power delivery is the problem leading to retriggering. Work for a future session in the shop. 

DIAGNOSING FAILURE OF WRITE

With all the changes, patches, bodge wires and resoldering attempts, the board will not trigger on +Storage Write anymore, thus I can't write new data patterns to do my testing. I put one scope lead on the output of the RC network for the signal, also serving as the scope trigger. a second probe on the Q output of the first write timer chip U12, a third probe on the Q output of the second write timer chip U13 and a fourth on the NAND gate that produces a logic low -W for the MRAM chip when the second timer chip pulses high and +Storage Write is still high. 

The scope trace showed me that the trigger is activating as it should but the first write timer chip is not triggering. I tested connectivity on the pins of the chip, which all appear to be working correctly. I didn't spot the cause by the time I had to leave the workshop, but I will keep working on this until I figure out why the chip, previously working properly, stopped sometime after I did some resoldering on the chips. 

Continued testing 1130 MRAM board - working on the retriggering

WIRED UP A TIMER TO SEE ACTIVITY ON ALL PINS

I tacked small wires on the pins so that I could watch the various pins to determine where the problem arises that results in the SN74LVC1G123 chip retriggering when it shouldn't. First I watched the VCC and ground rails at the chip to see if they were contributing to the problem, but they were rock solid.

I then focused in on the retriggering and noticed that from time to time, I would get a single pulse but mostly repeats. I zoomed in and looked at what might be different when it didn't retrigger. I saw that the input signal +Storage Read at the output of a NAND gate rose for a very brief time right as the second timer in the chain emitted its short pulse. When the dip was 2V or less, there was no repeat, but if the dip dropped further, the chip fired again. 

Yellow - trigger, green output, purple second timer output

yellow - inverted trigger, blue output, pink RC node

INTRODUCED FILTER TO SWALLOW THE BRIEF DIP

I added an RC network between the +Storage Read signal coming from the cable and the logic circuits that fire the timers and control other devices on my board. The initial filter was set conservatively with a time constant of 4.7ns. 

It was working pretty reliably so I introduced another network between +Storage Write and the logic using that signal on my board. When I tested, a few times I didn't see the timer trigger at all during a write. I also saw the read timer begin to retrigger from time to time. 

Tomorrow I will make the RC time constant bigger to see whether this quenches the retriggers. Will also dig even further into the behavior of the timer chip - both the first read timer and the first write timer - where the retrigger occurs. 

What I noticed is that the retrigger happens on the first of two timers in each chain, but not on the second. That is, the circa 100ns pulse emitted by the second of a chain does NOT retrigger while the circa 800ns first timer output is where the retrigger occurs. This further bolsters the idea that the issue lies in the trigger signal to the first timer. 

Continued testing 1130 MRAM board - dealing with the signal bounce and retriggering

HAD LARGE TRACES FOR 3.3V, GROUND, PLUS GROUND PLANE

I over-engineered the size of the traces to deliver 3.3V around the board as well as deploying a ground power plane. Decoupling capacitors very close to each chip are also a feature of the design. However, if the regulator can't instantaneously deliver enough power when many gates switch, particularly the 8ma sink required for each of sixteen sense bits and two check bits, then it could cause the sags and anomalies I was observing. I had what I believed was adequate buffering already, but I tried to bump it up.

BUFFER CAPACITOR ADDED

I tacked on a 470uF capacitor across the 3.3V and ground rails to give the board a bigger buffer for energy delivery. The final design would have an SMD version placed neatly on the board, but this is a rework of my current PCB thus I added a through hole part. 

No change when I tested. The +Storage Read signal had a glitch in the middle just when the first read timer ended and the second timer started its pulse. The first timer immediately retriggered. When the word being read had many bits that were one, the retriggering would continue for many more cycles, but when the data word was all zeros I only saw one retrigger. 

BYPASSING THE LOW SIDE MOSFET

The next theory was that my decision to use a MOSFET to isolate the 1130 ground from my board when not powered was introducing a problem. I jumpered around the MOSFET so that the ground was direct, yet the issues remained. The signal was slightly less bouncy but still enough to retrigger. 

ADDED TERMINATION FOR THE SIGNAL

The signal looked relatively clean except for the glitch at the time the second timer was emitting its pulse. With 74HC series chips there is generally no need to do impedance matching, particularly with relatively slow signals as in the IBM 1130. However, the cables that IBM uses with Solid Logic Technology (SLT) machines such as the 1130 are designed with 95 ohm impedance. 

I matched the impedance of the signal to see if that would clean up the signal, but it made no difference. So far I have been trying everything I can think of to stop the bad behavior.  Reading out a word of 0xFFFF will fire off eighteen sense bits (the word plus two check bits) thus sinking about 150ma over 100 nanoseconds. 

WATCHED THE +STORAGE READ SIGNAL AT ITS SOURCE

I put a scope trace on the source gate that generates the +Storage Read signal, before it ran across one backplane and over a cable to a different card compartment and then over cable T3 to my board. The signal looked the same at the source. I find that suspicious. Next time I am in the workshop I will remove the PCB entirely and watch the signal at the source again. If the glitch is coming from the 1130, I would have to address the problem differently than if it is a weakness on my board. 

Side project - MV864A meter restoration - almost complete schematic produced

FINISHED THE RANGE ATTENUATOR WIRING AND PART NUMBERING

The numbers for the resistors were completely changed from the version in the manual, but they were mostly in the same arrangement. The values were changed a bit, with my version using standard resistance values while the newer version in the schematic took advantage of more diversity in values available later on. 

ONE MAJOR QUESTION REMAINS TO BE ANSWERED

The version in the manual uses a constant current source produced by a transistor in the power supply to develop a voltage drop across resistors being tested by the meter. I don't know where my version gets the voltage to deliver to the resistors under test, as I don't see zener diodes, transistors or other parts that would act as a constant current source. I will have to trace out the wire from the function switch section C wiper as that is where the supply for resistance testing is delivered. 

THE SCHEMATIC IS ESSENTIALLY COMPLETE EXCEPT FOR THE QUESTION ABOVE

I HAVE WHAT I NEED TO TEST, RESTORE AND  CALIBRATE

Since I know the circuit design, parts numbers and test points for my version, I can use the calibration and diagnostic methods from the manual to get this meter in perfect shape. 

Continuing testing of the 1130 MRAM board

REWORK DONE TO THE BOARD AND REINSTALLATION ON THE 1130 FOR FIRST TESTS

I lifted pins, added jumpers and wires, to resolve the design flaw I had discovered. The repaired board was put back on the IBM 1130. I then did some Load and Display tests with the logic analyzer connected to validate the behavior for these simple cases. 

It was still producing spurious sense bit outputs. I switched to the oscilloscope for an analog view of the signals. The spec sheet for the SN74LVC1G123 timer chip indicates that a logic low is 0.8V or lower and logic high must be 2V or higher. The unasserted state of the +Storage Read signal is around .2V and it sits around 3V when active. 

However, I can still see retriggering of the timer. The yellow trace is the +Storage Read signal, the green signal is the first time which delays about 800ns and the purple signal is the second timer which produces an 100-120ns pulse. The pulse is what generates the -Sense Bit X outputs. 

I can see the first timer immediately retrigger around the middle of the trace, thus the second timer produces more than one pulse. There is some funniness on the +Storage Read signal right as the second timer fires, which dips down low enough to look like a logic low. Thus as it recovers, the first timer fires anew. 

As a clue, when the word being read is all zeroes, the pattern above occurs. Just two pulses (one more than desired). However, when the word is mostly ones, the retriggering seems to continue long after +Storage Read goes back to low. 

I have to mull over how this might be occurring. I did fix the vulnerability where a machine cycle shouldn't send out sense pulses because +Storage Use is low. Whatever is happening here is not that condition. 

This may be an issue with inadequate ground conductance causing some bounce in the levels when many gates are switching, or perhaps I need to bump up the capacitor at the output of the 3.3V voltage regulator. 

Side project - MV864a meter restoration - simulations and look at the non-board wiring

SIMULATED PREAMPLIFIER AND DRIVER OUTPUT SECTIONS

The photoisolator component has twin photoresistors that are driven by two LEDs. The LEDS oscillate at 94Hz, thus the resistors should pick up the 94Hz signal, with the input to the meter driving the photoresistors. 

The current flowing through the photoresistors is detected by a MOSFET and a string of amplification stages, giving the 94Hz signal at an amplitude based on the input voltage. That is then further amplified by the driver output circuit. The signal from the driver output circuit is rectified to turn a positive and negative cyclic signal into a stream of positive pulses. 

The positive pulses are mixed with the original 94Hz source in the synchronous demodulator to recreate a DC voltage that is an analog to the original input signal. This also detects whether the input was negative or positive and causes the output of the demodulator to take the same polarity. 

LTspice does not have a photoresistor model. In addition, I had to model the effect of the LEDs producing the 94Hz alternating positive and negative square wave. Since I have no specs for the LEDs, photoresistors nor the MOSFET detector, I had to guess a bit to produce a reasonable result from the circuit. 

I used a voltage source to generate what the photoresistors would pass into the MOSFET, consistent with a current from the input flowing through them modulated by the change in resistance as the 94Hz light from the LEDs hits them. The circuit simulated properly, thus I believe that everything except the synchronous demodulator checks out. When I simulate that part, I will feel confident in the schematic I captured by the reverse engineering. 

LOOKED AT DISCRETE CONNECTIONS ON THE METER

I began to trace out the wires coming from the main and power supply boards. For each wire, I noted the color and its destination. As I did this, I looked closer at the Range Attenuator and Function switches. My working assumption was that the range attenuation and function switching wouldn't have changed more than trivially between the version I have and the schematic shown in the manual. To my dismay I discovered the differences are more substantial.

CHANGES IN THE ROTARY SWITCHES FROM MY VERSION TO THE MANUAL VERSION

The Range Attenuator switch in the manual has eleven sections of 15 positions, but the meter I own has only nine sections. The Function switch has 7 sections, just like in the manual, and it matches. I am going to have to dig in and reverse engineer this to see how it has changed. 

The last two sections seem to match between the meter I own and the manual schematic. Wires run to the back panel that has all the calibration potentiometers to adjust each of the fifteen ranges so that the meter produces the correct reading. Other than changes in the component numbering between the versions I believe it is identical. 

Calibration board on right, wires to Range Attenuator switch

I began to label all the components from my photos of the actual meter, so that I know the parts number of each and can apply that to the reverse engineered schematic as I bring the copied over schematic part from the manual into agreement with the actual wiring. 

IBM 1130 MRAM memory board - root cause of the unwanted stream of pulses from the board being corrected

REALIZED THE CAUSE

I had made a tweak which I thought optimized my design, so that the timer pulses that control emitting the sense output bits are triggered by the rising edge of the +Storage Read signal. On the surface that seemed logical, as we only want to fire them off when we are doing the read portion of a storage cycle.

However, the genesis of the +Storage Read signal is when the IBM 1130 is in clock states T4, T5, T6 or T7. This happens on every machine cycle, not just during memory access. Thus, we would trigger the pulse to emit sense bits on the second half of every machine cycle, not just the ones we want. 

The +Storage Use signal is what indicates that a particular machine cycle involves a memory read. Thus, I should have triggered this when both +Storage Read and +Storage Use go high. Originally the design did use this logic, but to save gates I switched to simply using +Storage Read, forgetting that this is not just raised during a read attempt. 

RESOLUTION OPTIONS

There is one spare gate on a 74HC00 chip, a NAND, that I could press into service to make a signal when both +Storage Read and +Storage Use are high. The original design used this gate plus another that inverted the output to produce a positive going pulse as the trigger to the timer chip's notCLR input. I needed another gate for a different change so I made the ill fated decision to drop the +Storage Use from the trigger conditions. 

The solution is to use the spare gate on U14 to produce a low output when both +Storage Read and +Storage Use are high. The timer has three control inputs - ~A, B and ~CLR - which have to be reconnected. There are three ways the timer can be triggered - 

1. a rising edge on ~CLR while ~A and B are L and H
2. a rising edge on B while ~CLR and ~A are H and L
3. a falling edge on ~A while B and ~CLR are H and H

 The original design used option 1 but I only have a falling edge from the added NAND gate, so I have to shift to option 3. Thus those three control pins have to be rewired (actually only ~A and ~CLR but for technical reasons I change all three. 

Of course I could redo the board, waiting a couple of weeks for parts and the new PCB, but that is punishing. I instead looked for ways I could rework the existing board to function as intended. I did figure out a way to rework the board. 

It involves lifting six pins total from two chips to disconnect them from the existing board traces. Mainly this is due to traces running underneath the chip not just off to the sides, so that cutting traces would be more of a challenge. I then add some jumper wires across pins and over to the +Storage Read pin (cable T3 pin lower 6). 

REWORK STEPS

I have to lift pins 5, 12 and 13 from chip U14 (the quad NAND device) and pins 1, 2 and 3 from chip U5, the timer device. This isolates the pins from the existing connections on the board traces they had been soldered to. 

I then put short jumper wires between U14 pins 1 and 13, as well as 5 and 14. I then add a wire from U14 pin 11 (output of our NAND gate) to U5 pin 1.  On chip U5 I add short jumper wires from pin 8 to pins 2 and 3. Lastly, I run a wire from U14 pin 12 and the connector for cable T3, on the lower position 6 (+Storage Read). 

The schematic version of the rework is to disconnect the +3.3V connections to chip U14 pins 12 and 13, the previously unused gate. Wires run from these pins to cable T3 lower 6 (+Storage Read) and to U14 pin 1 where the +Storage Use signal is connected. 

Over at the existing connections to chip U5, we disconnect the three existing control signal connections.

Jumpers tie pins 2 and 3 to +3.3V while we run a wire from U5 pin 1 over to U14 pin 11 where our new control signal is generated. 

GOOD VERSION OF SCHEMATIC AND PCB LAYOUT

IBM 1130 MRAM memory replacement - investigating Parity Check and random data occurrences

LOGIC ANALYZER CAPTURE RESULTS

I hooked up the DSLogic analyzer to the 1130 to capture key signals allowing me to figure out what is going wrong with the read and write process and the phantom parity check issues. The device can sample up to 16 lines at a time, which is not enough for a full capture of every signal of interest, but should allow me to watch subsets until I spot an issue that hints at where to zoom in. 

If I had unlimited channels, I would capture:

• all 16 B reg values. 
• all 16 sense bit outputs
• check bit 1 and 2 sense outputs
• storage read and storage write commands
• T0 to T7 clock pulses of the 1130
• parity check detection signal
• all 13 SAR values going into the board

I began with sampling  some timing related information to see if I am doing things at the wrong time. I grabbed storage read, storage write, T0, T2, T4, T6, the parity check signal and some sense bit outputs including the check bits. If the sense bits are being produced at the wrong times, e.g. too late in the read cycle when we are already starting the write, then it might lead to the conditions I am observing. 

Doing a read of a word that is all zeros produces the correct data without a parity check, but when the word has bits that are a one, I saw that the board then was emitting a continuing stream of bits long after the read was completed. 

FAILURE MECHANISM

The circuitry for the B register will set the bit to one if a pulse arrives on the sense bit lines - any time that it arrives. It is not gated to only activate during the time of a read, it will flip on the bit whenever it arrives. Thus if my board emits sense pulses it is going to stomp on the B register. 

Why this is happening was not immediately obvious. I put a timer chip on a breadboard and tried to cause it to fire off a stream of pulses but couldn't create a plausible sequence to make this happen. The chip I am using on the board, sn74lvc1g123, is a retriggerable timer, thus it can produce a stream of repeating pulses in the correct circumstances. 

I will have to do some analog investigation, as the issue might be noise, invalid logic levels or other issues that won't show up on the logic analyzer. 

IBM 1130 MRAM memory replacement - continuity test, then testing on the IBM 1130

CONTINUITY AND SOLDER JOINT TESTING

I found one pin that appeared to be soldered well but lacked continuity - the output of the write timer circuit. Based on this I decided to do a more thorough test using the PCBite probes to check that each pin on a chip had continuity to the appropriate end points and that there were no shorts to adjacent pins. This was time consuming but worthwhile.

I came across about ten connections that looked like shiny good joints and the pin wouldn't move when pushed sideways, but electrically they were capacitors or open circuits. I carefully repaired every one of them.

I took the time to check many of the control connections and the memory address lines for good continuity. Once I believed this was likely free of bad connections, I moved over to test with the 1130. 

LIVE TEST ON THE IBM 1130

I plugged the board into the IBM 1130 in place of the IBM core memory compartment B-C1, connecting cables T1, T3 and T4 as well as +12VDC power. The machine was powered up and I could do some quick tests. 

Using the rotary mode control set to Load and to Display, I can load chosen patterns into memory and read the results. The pattern is toggled with the 16 console entry switches (CES) and the results show on the display panel as the Storage Buffer Register output. dete

I saw a few spurious Parity Checks - which should never happen because the two parity check bits are created on the fly by my board based on the memory contents. Mostly the memory was storing the data I set on the CES and retrieving it when requested, but there were those phantom Parity Checks to consider. 

I then used the Storage Load and Storage Display functions that are available to the repair engineers - these let me set a pattern on CES and loop repeatedly through memory setting that into every word. Once done I could perform the Storage Display and loop repeatedly reading memory. During these events I found a few more phantom Parity Checks. 

More disturbingly, when I went back to use the rotary mode to display locations, after having set every word to FFFF, the data coming back was somewhat random, not the pattern. 

FIRST THEORY

I suspect this is a timing issue, because the detection of a parity check occurs during the write portion of a storage cycle, when the data should have been established along with its chosen parity by some logic in the CPU. It could also be a continuing issue with reliably triggering the B register flip flops with the sense output pulses. 

I will have to set up a logic analyzer to capture key signals while I run some Storage Load, regular load, Storage Display and regular fetches from memory locations. That will help me focus down on the area having problems. 

Side project - MV864A meter restoration - blocking out entire schematic

USING EXISTING MANUAL SCHEMATIC TO BLOCK OUT NON PCB PORTIONS

I chose to use the schematic in my manual, which is too modern to match the version of the meter I own, to block out the remaining functions most of which are not on the two printed circuit boards. This includes the Range Attenuator, the Function switch, the Meter, the input jacks, the zeroing pot for the meter and the pot to adjust the full scale resistance reading to 0. 

The components used for the Range Attenuator sit on the power supply PCB and are joined to the rotary switch via wiring. I used the manual version of the part numbers for the parts that will be on the power supply PCB for now. This is because the part numbers on the board don't match between the manual and the actual meter I own. As well, the numbering scheme for the rotary switch, function switch and other parts that are not on a PCB are different so I went with the manual initially.

I intend to trace out the actual meter to resolve all the numbering to match my actual meter. I will also catch any changes in the circuit that exists between the manual version and my schematic. I don't expect many differences in this part of the device but we shall see. 

NOT DONE WITH THE RANGE ATTENUATOR YET

I put in quite a few resistors and connections for the range attenuator but have not finished yet as it is tedious work with many parts that have to be wedged into the schematic around the rotary switch sections. I did complete the Function switch.

REMAINING WORK OTHER THAN RANGE ATTENUATOR AND MATCHING MY METER

I have to put in the output connector on the back that delivers a 0-1V output matching the meter deflection. The pot to zero the meter is not yet implemented. 

I then have to rationalize a connection from the Function switch to the power supply which in the version from my manual is passed a fixed current produced by the power supply. My reverse engineered power supply does not have a current source like this, so this will be a notable difference between the manual and my meter. The current is applied only in the resistance function to power the input jacks so that a voltage drop is generated on the resistor under test, which is then measured by the meter.

SCHEMATIC SO FAR

 

Side project - MV864A meter restoration - simulating the DC Modulator Driver that produces 94Hz chopper signal

TRYING TO TEST SECTION BY SECTION USING LTSPICE SIMULATION

I started with the circuit that should be oscillating at 94Hz, producing square waves on LEDs inside the photoisolator component. This part of the circuit is called the DC Modulator Driver.

The light from the LEDs falls on two variable resistance photocells in that component, which are biased by the input signal to the meter and then amplified. Ultimately, the meter will compare the output of the oscillator with the detected but biased signals to capture the results of the input. 

I found an error in my schematic but after correcting it, I was still unable to see oscillation of the circuit. The manual's schematic has a different design using silicon transistors rather than the germanium ones in the actual meter I am restoring. I captured the DC Modulator Driver circuit from the schematic in the manual but that too did not oscillate. If it had worked but my reverse engineered version did not, it would focus me on possible errors or inadequate modeling of the germanium semiconductor devices. 

Since neither works, I have to find the root cause of the failure. It may be some missing components inside the photoisolator component, which is a sealed can that the manual insists should only be serviced by Millivac. I do know that the meters work in real life. 

GETTING THE MORE MODERN VERSION IN THE MANUAL TO WORK

A mistake in drawing the circuit of the manual's version of the DC Modulator Driver caused it to produce the 94 Hz output I expected. I tied on side of the oscillator output to the bias voltage source, which caused the opposite leg to produce 94Hz. However, when I corrected the drawing the simulation once again flat-lined. 

That was a clue. Turns out the value of the inductance, the four resistors in the photoisolator component and the bias voltage setting on the pot are all inter-related and must be in certain ranges to achieve oscillation. 

GETTING MY REVERSE ENGINEERED SCHEMATIC TO WORK

I discovered that the signal transformer was quenching the oscillation - when I removed the transformer I got my 94Hz square waves but oscillation didn't happen with the coil in place. I don't have specifications for the coil that I had to take wild stabs at inductance to find a value that allowed the transistors to oscillate. 

It could be that the transistor model I used didn't have enough oomph to oscillate, since I also don't have specifications for the 2N1373 germanium transistors I found in my meter. Also lacking were the resistance values in the photoisolator and the LED characteristics. 

PASSED REASONABLENESS TEST

Since I could achieve oscillation with generation of the square waves with certain component values, plus knowing that the real meter works so it is definitely oscillating, I knew that the schematic I derived was now representative and correct. 

Construction of new 1130 MRAM memory board completed

BUILDING THE NEW BOARD

I used my hot air rework tool to remove the parts that were to be salvaged from the old board. These were still part of the design of the new board. For each, I removed it carefully and then soldered the part onto the new board. 

This included the gold pins that form the connector that the IBM 1130 cables are plugged onto. For this, I used the soldering iron and pushed the pin up a bit so that I could then grip it with pliers and remove it while heating again. I use a spare socket to push the pins into, ensuring the 24 pins are aligned properly when I solder them down to the new board. 

I examined the board closely with the microscope, pushed on leads to ensure a good bond for each pin to its pad, and did a few continuity tests including validating there was no short on the main power rails on the board. 

I had to return home to wait for a delivery (an area rug was cleaned by an outside service), but will attach and test on the 1130 system when I get back to the shop. 

PCBs and parts are on hand - beginning construction of new 1130MRAM board

EARLY ARRIVAL OF PCBS

The delivery estimate for the new version of the memory board was Friday afternoon, but I was pleasantly surprised to receive it early this afternoon (Thursday). That was the last part I was waiting for in order to build what is hopefully the final version of the board and put it into the IBM 1130 system. 

BEGAN BUILDING NEW BOARD, INVOLVING MOVING PARTS ACROSS FROM OLD BOARD

The design has some new parts on it, both in the power supply area and for the Sense bit output circuits. I first installed the power supply and checked its operation before installing the rest of the circuitry. It gave me a reliable 3.3V supply for my circuits and isolates the ground when power is not applied so that there is no back feed of voltage from a partially energized 1130 into my board. 

The bulk of the construction will take place tomorrow, but I was able to install two of the timer chips that produce an 80-100ns pulse delayed 800 ns from the trigger event of a write to memory. The timer chips are very small and a challenge to solder, but I got them on and validated good connectivity for each lead without any shorts to adjacent pins. 

Side project - MV864A restoration - substantial progress in reverse engineering

POWER SUPPLY SCHEMATIC VERIFIED WITH LTSPICE SIMULATION

I had some errors in the schematic I drew for the power supply, which I identified when I began simulating the power supply in LTSpice. I had to invent a few models for the germanium transistor and RA1 reference amplifier, as well as dropping everything from the main transformer back to the wall plug, then put some resistors as loads for the -14.5VDC, -6VDC and the AC supply for the power on lamp. 

The result is a high confidence schematic for the power supply:

MAIN BOARD CAPTURED IN A SCHEMATIC

My drawing of the main board components is done but I have not yet done LTSpice simulation of the sections to validate my work or spot errors. Simulating transformers is a bit hokey in LTSpice, particularly a schematic with five independent transformers most of which have center tapped windings. Instead, I will replace the transformers with voltage/signal sources and inductors as the output load so that I can watch each section perform its role. 

DRAWING THE RANGE ATTENUATOR AND FUNCTION SELECTION CIRCUITS

The range attenuator selects the proper range for the input voltage, current or resistance, with fifteen steps or levels. It is implemented with a complex rotary switch having eleven sections with fifteen contacts apiece. This switches resistors to reduce the input to a standard level that the rest of the circuit is designed to handle. 

The function selection circuit has six positions - off, + voltage, - voltage, +current, =current and ohms. This rotary switch has seven sections with six positions each. I am about halfway through the range attenuator capture at this point. 

WILL CAPTURE INTERCONNECTS BETWEEN BOARDS AND CONTROLS

There are quite a few wires that run from the rotary switch to the two PCBs - as the power supply PCB has many of the resistors on it that are part of the range attenuator, it has the most wires connected. There are also a number that run from the input jacks and the main PCB to the range attenuator. That will wrap up the work reverse engineering this meter. 

Side project - MV864A restoration - reverse engineering power supply section

 WAITING ON PCB AND PARTS TO RESUME MAINSTREAM 1130 ACTIVITIES

The 1130MRAM memory PCB is scheduled to arrive on October 10th and the new components will be here on the 8th. Until I have the new board ready to final testing on the 1130, it does not have working core memory. That is required to begin testing the 1132 printer and 2501 card reader controller logic as well as to resume testing of my virtual 2315 disk cartridge project. 

In the interim I will keep busy doing these side projects - the Millivac MV864A meter and the IBM 3278 terminal restorations for example. It was worth $28 to speed up the delivery of the PCB, since I am eager to work on the top priority 1130 restoration tasks. 

POWER SUPPLY VASTLY DIFFERENT FROM THE MANUAL AND SCHEMATIC

The manual shows a power supply with four silicon transistors, four diodes, a zener diode, an LED for the main power indicator and three test points to measure +8.5V, -6V and ground. The actual board in my meter has one transistor-like device plus a large germanium power transistor, two diodes, and an incandescent main power indicator. 

Even odder, the three test points I found, marked TP63, TP62, and ground, measure -14.5V, -6V and 0V respectively. There is an 8.5V delta between the first two, but nothing shows up as +8.5V. The meter appears to work, thus this must not be a result of failure in the supply. Rather this is likely due to the older germanium technology used on my meter versus the redesign with silicon semiconductors. 

CHALLENGES FINDING DATASHEETS FOR BOTH TRANSISTOR DEVICES

I have completely failed to find any data sheets for the MHT3030 power transistor, although it is almost certainly a germanium PNP device. I did find the smaller device, a General Electric RA-1, in an old GE manual found on the web. It is a compound device, four terminal, with a transistor plus a zener diode attached to the transistor emitter. It was used in voltage regulator circuits and there are reference designs in the GE manual. 

This manual "GE Transistor Manual - Circuits, Applications, Characteristics, Theory" published in 1964 is a gold mine of information. The section on Regulated DC Supply and Inverter Circuits covers the Reference Amplifier (RA) devices and circuits using them to build 'precision' voltage regulators. Here is the sample circuit in the manual:

This corresponds extremely well with the recovered design from my reverse engineering. A few differences - the meter uses a half wave rectifier rather than the full wave design from the GE manual and the GE manual uses a fixed resistor voltage divider to provide the 7V reference voltage to the RA1 base when the output is (almost) 12V. 

Due to resistor tolerances and a more limited choice of resistor values in the 1960s, GE chose the resistors to give 11.73V which was the close enough (for a 'precision' voltage regulator). The inclusion of a potentiometer in the Millivac circuit allows for adjustment to hit a target output voltage, with the midpoint of the pot setting -14V and enough range to achieve -14.5V. 

Here is the schematic I created from reverse engineering the board of my meter:

Two things remain a mystery to me after this work. First, the method of creating -6V appears to be a simple voltage drop over 540 ohms of resistance - this only works out to an 8.5V delta if the current through the resistors is 15.7ma. Until I see how this line is connected on the other PCB I can't assess whether this makes sense.  Second, the existence of -14.5V and -6V rather than the +8.5V and -6V of the manual's power supply. 

Here is the schematic from the manual for comparison:

Side project - MV864A restoration - reverse engineering challenge

PICKED UP MILLIVAC MV864A AND PAID FOR MANUAL FROM THE MANUFACTURER

Having purchased a used high accuracy meter on eBay, it was time to restore and calibrate it so that I can use it on my bench. It generally works, but when I used my bench power supplies to deliver given voltages and currents to compare with the meter reading. The readings were close but not exactly on. 

This meter has a grid of potentiometers on the rear which allow for calibration of each scale of voltage, current and resistance. I found that on some ranges I couldn't get the meter all the way to the target reading even at the extreme of the pot movement. I also didn't know if I had to do the calibrations in a certain sequence or could adjust any scale independently of the others. 

I contacted Millivac and asked if I could buy the manual that has the schematic and calibration instructions. I provided the serial number of the unit to have them find the proper version of the manual. I was told that the oldest manual they could provide was for a newer version but that the schematics and other information should be quite close. I spent the $100 and began the restoration when it arrived - see earlier posts about this side project for details. 

MAJOR DISSONANCE BETWEEN MANUAL AND THE UNIT ON HAND

Unfortunately for me, the schematics and other diagrams are very different - you can see that the general scheme is the same but the parts used and layout were very, very different. The major reason is that my unit uses primarily germanium transistors whereas the manual shows the meter after they had re-engineered this around silicon transistors.

The parts numbers are all different, because it was a redesign. The layout on printed circuit boards is different. In order to put a scope or voltmeter on various points to compare against the values shown in the manual, you need to know where the point sits. Further, the waveforms and voltages likely have changed between the germanium and silicon designs. 

Here is the portion of the schematic that I have been reverse engineering - I still have a few values to add to the drawings and some cross checking, but it is close. First, the portion of the schematic from the manual. 

Next is the version I captured from the actual unit:

Lets zoom in one two sections to see how different they are. First we will look at the input filter that sharply notches powerline noise. Second we look at the preamplifier that finds the difference signal between the filtered input and a reference signal from the photocells of the chopper. 

For the input filter, I have the following component values and connections:

Compare that to the schematic portion from the manual. These parts should be very close since a notch filter has component values determined by the frequencies and rolloffs, which wouldn't depend on germanium versus silicon techology at all. In other words, this is the best situation for a match.

Even here we have a few discrepancies in the values of parts although most are close. The output resistance is much higher, which may be based on the change in transistor technology. The parts for the filter are visible on the board:

The variations would be tolerable here, even if I had to map out that 3R1 on the manual schematic is R201 on my PCB. Once I move into the areas where the redesign is more substantial, this becomes less feasible. 

The preamplifier as I found it on the unit has a germanium FET and two germanium 2N414 NPN transistors. 

The manual has a more complex circuit with the same FET but three silicon 2N2907 NPN transistors. I am guessing that they chose a lower gain for the three stages to achieve the same result as the two germanium transistors provided on my unit.

DIVERGENCE IS WIDENING AFTER THIS POINT

There are ten silicon transistors on the rest of the schematic and two coupling transformers in the version in the purchased manual. However, on the actual unit, there are fifteen silicon transistors and four coupling transformers. A second adjusting potentiometer is on my board, but not in the manual; it has no marking on the PCB to hint at its purpose. 

Here is the top of the PCB with the previously discussed sections partially covered to show the remaining components that must be reverse engineered. 

REVERSE ENGINEERING IS TEDIOUS BUT STRAIGHTFORWARD

The huge advantage I have is that the PCBs in the unit are single sided - traces only on the bottom and components only on the top. I have flipped the picture of the bottom so that I can match it to the parts in the top picture, allowing me to figure out the wiring between parts. 

I will keep at this until I have the entire schematic of this PCB captured. I figure I can use LT Spice to figure out the corresponding voltage and waveform values I should see at the reference points to correspond to the ones marked on the manual's schematic. 

In addition to this PCB, there is a second PCB that has the power supply and range attenuator components. This also is different from the manual version. Therefore I have to reverse engineer at least the power supply portion. The range attenuator and the front panel selector switch should match up fairly closely, so I won't bother drawing that out unless I run into problems during restoration that indicate a divergence.