I updated my built-in test generator, which had been built to create input for the ReadClock and ReadData lines while I was testing the disk driver version. It now produces input for the WriteDataClock line.
I also added logic that will turn on the WriteGate signal for a portion of each sector when I push either of two buttons on the fpga board. One button will begin writing only for the data record, while the other will write during both the label and data records.
I wired these generated signals to the inputs they will drive and began some testing. I first loaded the board with the XMSMALL disk image, ran without any updates and verified that the image in memory remained untouched. Second, I would triggered an update of the data records of sectors, uploaded the memory image and checked to see if I had altered just the intended words.
I did make changes to the logic involved in memory access in order to add in the sector updating/writing logic, so that is the first place to look. I might need to organize some diagnostic output that can be captured on the logic analyzer if I don't see anything obvious.