Please be patient - back to blogging soon

In the time since my last posts I have been very busy on a ton of small activities that lured me away from continuing the tape drive restoration. I expect to get back to work on the drive soon.

Among the activities that arose were:

• Holidays wherein I had to give up workspace to accommodate visitors
• Picked up and restored a TRS 80 model 100 computer
• Worked on reverse engineering and powering up a Soyuz capsule clock
• Repaired four ASR-33 teletypes
• Restored IMSAI 8080 computer
• Returned our two leased Hyundai cars
• Picked up a new Hyundai lease for my wire
• Picked up a Tesla model 3 lease for me

Methodical testing of Control Logic board - part I - movements

PUTTING THE DRIVE INTO READY STATUS AS PRE-THREADED TAPE

It is possible to thread tape manually through the machine and onto the take-up reel, then press the Load/Rewind button. This should advance the state machine to the DUMP state where the two reels rotate to feed tape into the vacuum columns. I set the BOT and EOT photocell inputs to the state if a tape were blocking the path, pushed the L/Rew button and saw the machine enter DUMP for 2.5 seconds.

Once the tape loops are sitting in the middle between the sets of photocells, the IN-LIMIT signal is generated which stops the load process and allows the drive to be made ready by pushing the START button. This should mark the drive as online and ready. It would then accept commands for movement.

Accomplishing this requires a bit of dexterity. IN-LIMIT must be off when the L/REW button is pushed, but after a couple of seconds when it goes into DUMP state, IN-LIMIT must be made ready.

To simulate the START button, I brought the input single low and then the circuit logic indicated my drive was online and that the READY lamp would be lit. At this point, it is primed for movement.

However, when I looked at the movement status outputs, the board was still commanding reverse, as it was still seeking the BOT tape. I had the signal active, but the logic for finding this requires that EOT be off at the same time. I tried to drop the EOT signal while leaving BOT activated.

This worked! The drive was still READY but the reverse movement stopped, the brakes were put on and it sat waiting for commands.

DRIVING VARIOUS MOVEMENTS ON THE DRIVE

The controller for the tape drives can issue commands to move forward, move in reverse, rewind, and unload by asserting input pins to this board. The action should continue as long as the command is asserted. In the reverse direction, it may be stopped by the BOT signal unless I deactivate it.

It took a couple of tries to get all the input signals hooked up and timed as needed to set up the drive as ready. That allowed me to reliably set up the motion tests below. While doing that, I found that any reverse movement was blocked by the brake on latch. I had suspected it was due to a bad 96L02 chip, but I see that the latch is being forced to reset by a bad NOR gate.

Chip U4B, a 74LS02 quad NOR gate, has pins 11 and 12 low (appropriately) but the output is also low, not high. Unless I could find a short somewhere on the board, then I had a bad chip. I flipped the board, inspected and did some basic beeping. It turned out to be a shorted input on a different chip, one which I had to replace and documented in a prior post. That was repaired.

I moved on to a more methodical checkout of the board, to verify the sanity of outputs, toggling the machine to various forward, reverse, rewind and other conditions, and stepping the loader state machine from REST until the drive goes ready.OFFLINE TESTING MODE

In addition, if the drive is not online, a pushbutton can enable the internal movement tester on the board. It can then move the tape forward and backward by pressing other buttons on the board. To accomplish this, I have to go through all the steps to ready the drive EXCEPT for the ON-LINE signal from the Start button.

Then, a pushbutton on the board will set the board into tester mode. First I verified that it accepted the tester mode push, then used the two directional pushbuttons to validate movement was being requested of the capstan logic.

This worked great - the tester drove the forward and reverse direction command outputs that control the capstan pre-amplifier. I didn't spot the forward command driving motion but after tracing through the chain of logic gates I found another gate whose output should be on but it wasn't.

It was one of the 74LS08PC quad AND chips, although drawn as an inverted OR. Trouble is, an OR of inverted inputs is not the same as an AND. They SHOULD have drawn it as an NOR of inverted inputs since that gives the same truth table.

Surprised it was misdrawn, I looked at other places where these AND chips were used to see how they drew them and found another place where they misrepresented it in the schematic as an OR or inverted inputs.

No wonder the chip output didn't agree with the inputs and the schematic symbol! It was working properly, thus my problem is in a different place than this gate.

AND gate on right side is incorrectly drawn as OR

When either of the inputs to the gate on the right above is low, it will drive the output low (thus should be drawn as a NOR with inverted inputs). That is the state I am seeing, which blocks the cyclic forward signals from the on-board tester.

The input 01 is high, since it is the notQ output of the rewind flipflop and we are not in a rewind. However, input 02 is low, driving the output low. The latch on the left is on, so the Q output (pin 5) is high. This drives the inverter output low(pin 15) which should cut off the transistor and make my NOR input 02 pull up to high.

In fact, regardless of whether the latch on the left is on or off, input 2 to the rightmost gate is always low. I have to zero in on those components and determine what has failed or is wrong with my test setup.

Transistor inverter

It is a pretty simple circuit - the gate of the transistor is pulled up to +5V with a resistor and then coupled through a diode to an open collector inverter (ULN2003) which either lets the gate float up at 5V or pulls it down to about ,6V, the voltage drop across the diode.

That means the transistor will be conducting in either case, pulling the output down. I don't see how this could switch off unless there is an applied voltage below ground level on the left side of the diode. After some research by my friend Ken, we discovered that this circuit counts on the diode voltage drop being around .45V, less than the .6 cutoff of the 2N2222 transistor. Not the best circuit in the world but it should be working.

Whether the input to the left inverter is high or low, the transistor remained conducting, pulling the circuit output low. I snipped the diode out of the circuit expecting that I would see +5 on the gate side, but it was near zero volts. We might have faults in an open R51 however it measures correctly. We might have a fault in C20 or in Q6.

Believing that a blown transistor is more likely, I removed it from the circuit and measured the voltages in the remaining components. All was as expected now, with both R50 and R51 showing +5V on both leads, while C20 had +5 and 0 on its two ends proving it wasn't shorted.

I grabbed a substitute PN2222 transistor and soldered it into place. It wasn't the same small round can format, but I was fine with the black plastic shape since it sat low to the board. After it was installed the malfunction began again.

Bad analysis on my part. I believe I have zeroed in on the cause and it is a fault in the left hand inverter. This is a darlington pair of transistors, acting as an open collector inverter. When the input pin is set to low the inverter does nothing and the circuit I am debugging will sit with the transistor conducting to produce a low output.

When the input pin of the inverter is set to high, the transistor pair should pull current to ground through the rest of my circuit, lowering the gate of my circuit until it turns off and the output becomes high. It is difficult to verify what is happening since the main action of this inverter is to be a current drain - a VOM isn't terribly enlightening.

What I chose to do was to apply a ground wire to the output of the inverter. That won't hurt the darlington pair at all, but will test the behavior of the rest of my circuit assuming the inverter properly pulls the output down near ground. I was pleased to see that the circuit being debugged would go high in this case. It appears the fault is in the darlington pair inverter.

The obvious next step is to remove the ULN2003 and replace it with a good one, but as a test of my theory, I can breadboard another ULN2003 chip and hook its output in parallel with the bad inverter. Applying a high signal to my breadboarded chip should produce the desired current drain and hopefully cause my overall circuit to operate properly.

Immediate snag - can't find another ULN2003 in my stock. I have to wait until Saturday evening to get the new chip, perform my test and potentially replace the bad chip.

Bad chip that I had already replaced - 74LS08PC

TRACING A DIFFERENT PROBLEM

I found my 'ready to move' latch on the control board being forced to reset but as I traced the signal back I discovered that it was due to a NOR gate U4G producing a low output with two low inputs. Rather than immediately pulling that chip, I looked for any evidence that the traces were being shorted to ground.

This NOR gate output hooks to two other chips, one of them is U2J that I had previously double replaced (first incorrectly and then to put in the right NOR chip). I looked very closely at the traces to see if my desoldering and resoldering had somehow shorted the trace to another one, but didn't spot anything.

Based on a hunch, I snipped the lead for pin 12 of U2J chip from the board and bent the leg up. It was still reporting a short to ground! That means I have a bad 74LS08PC chip and would need to replace this chip site for a third time. I fired up the board with that leg lifted to verify that the U4G NOR gate is giving proper outputs.

This time, I installed a DIP socket so that I never have to resolder again as the traces are quite funky after all the desoldering. That allowed me to beep out the connectivity and install rework wires before I had a chip in place.

I found that pins 1 and 6 should be connected but the trace soldered incorrectly onto pin 2. This required a small bit of rework under the board beneath the socket. I then had to address some misrouting of traces for pins 11 and 12, but once it was repaired, the board was ready to have the hopefully working 74LS08PC chip inserted into the socket.

Single shot chip takes a dive - not so amusing distraction

MYSTERY FAILURE OF CLOCK TRIGGER CIRCUIT

The following circuit is given a set of pulses with a 60Hz rate, which should produce properly shaped on and off times to feed into a 'ready for movement' latch elsewhere on the board. I found an unvarying high clock signal on the 'ready for movement' latch and traced back through the circuit to understand where it was failing.

Clock shaping circuit

The input pin 4 on the left receives the 60Hz square wave signal. It should produce an inverted clock out of pin 9 on the right, but all I had was a steady logic level. First up I checked the existence of +5 on pin 16 and ground on pin 8. Next I verified the input was good on pin 4.

The two reset pins, 3 and 13, should be held high and have continuity to pin 5. Check. All other components, two capacitors and two resistors, were wired properly. . I decided to beep out the entire circuit, just to be sure the diagram was accurate since I found the added 1K resistor R68 during prior explorations of the board. Unfortunately, the conclusion is that the 96L02 chip has failed. Valid +5V on pin 5 and square wave input on pin 4, but no action on pins 1, 2 or the outputs 6 and 7.

Time to buy a replacement, however there are none at Anchor or the usual online retails like Digikey and Mouser. Ebay purchase will add at least a week delay, thus hoping to find a faster alternative I started hunting other retailers. I found Vetco in Washington state who sold me one with USPS flat rate envelope delivery which ought to get it to me later this week

Putting the correct 74LS08PC chips onto the board

FIXING THE CLOGGED HEADS OF MY HAKKO FR300 DESOLDERING GUN

My desoldering gun sucks the solder through a fine opening in the tip, but it can easily get clogged. The tips I use, 0.8mm and 1mm openings, come with ramrods to help clean them but once a serious clog develops, the rod will no longer work.

The problem tends to happen with a bit of debris such as a chip lead is sucked into the tip. When solder forms around it and hardens, we no longer have sufficient suction to clear the solder out of the PCB holes.

I ordered two new tips but also bought a hand drill set with small drill bits that I can use to clear out the two original tips. When these arrived, I was able to drill out the 1.0mm tip but did install the new 1mm tip to use removing the wrong chips.

REPLACEMENT OF THE FIVE MISIDENTIFIED CHIPS

Removing the old chips was the time consuming part. Putting new chips into the board and soldering was quick. I was fortunate to have dozens of 74LS08PC (quad AND gate) chips on hand. Due to the two chip removals, I had some pads that had lifted from the board - typically where the pin has the trace on the top of the board but uses a pad on the bottom as an anchor. I decided to attempt to touch up the top side of the pins in question.

BEEPING TO VALIDATE CONNECTIVITY

Because of the potential for broken connectivity due to the lifted pads and other issues in the rework locations, I beeped all the connections from the 90 pins affected, ensuring that I still had connectivity after my second serial repair in this spot.

I needed 2 extra short jumpers in addition to the one that was previously added to U6J. I have full connectivity so the replacement back to the proper chips is complete.

TESTING RESUMES

My initial test was to see that the machine powers up in the REST state and with the BACKWRAP signal off (high). A push of the Load/Rewind button should advance the load state machine to WAIT state and force BACKWRAP to ground. If these worked, it suggested that I had a board in decent condition.

Indeed, BACKWRAP is now high, which means inactive, when the board powers up or is reset. When I 'pushed' the Load/Rewind button, I saw the state machine advance from REST to WAIT, which should have lowered BACKWRAP, but it didn't.

I looked at the logic involved and found that the WAIT state is only one of the three conditions that must be correct in order to take BACKWRAP to ground. The other two are CART-PRESENT, since when the operator uses a tape with an autothreading band the state machine does not back wrap. The third is TAPE-PRESENT, a signal that is active if either of the phototransistors that look at Beginning of Tape (BOT) and End of Tape (EOT) is switched on.

Since I have no connection to the phototransistor board, the default state is the same as having both light sources blocked. The drive interprets that as an attempt to do a Load/Rewind after power-up with tape already threaded through the drive. In that case, we don't want to try threading.

I wired a pullup resistor to the inputs for BOT and EOT, which eliminated the false detection of TAPE-PRESENT. This left the logic primed so that when the state machine does to WAIT, the BACKWRAP should drop to ground level. That is indeed what happens!

It is time for me to step back and map out a comprehensive test plan, first verifying the default power-up states of all the output signals. Next I can test the major functions of the control logic:

• Powering up while tape is 'in the tape path', then readying the drive
• Driving forward both via input pin and by the test buttons on the board
• Repeating with reverse, both by test button and input pin
• Verifying operation of rewind command from input pin
• Trying Unload button and watching the behavior
• Trying Load/Rewind on ready drive, watching behavior
• Stepping through the load sequence for non-autothread cartridge
• Stepping through the load sequence for autothread cartridge
• Stepping through the load sequence for mini-reel

In the load sequence tests, I want to test both successful attempts and time-outs to insure that the state machine is working properly. This will involve simulating changes in input pins at specified times. 

Beeping out the rest of the Control Logic board to verify traces and schematic, found a big problem

MISSING AND BONUS COMPONENTS VERSUS SCHEMATIC

I spent some time reconciling the components found on the PCB and in the schematics. Once I had my spreadsheet in good shape I was able to quickly locate parts for beeping out connections.

I discovered quite a few that were on the schematic, in the range of R82 to R88 along with associated capacitors from C64 to C67 that were not on my board. Where these parts were shown on the schematic, straight connections existed.

Two resistors, R80 and R81, were added onto my board as a rework in an unprofessional style that led me to believe that the prior owner added these on their own. Another component R77 on the PCB was found to be in line with a connection that is a straight wire on the schematic, thus it was deleted in later boards.

R80 added under U1B

R81 added with tubing and loose resistor

I also found that resistor R76 was not on the schematic and the board has a 0 ohm resistor installed, thus this was a rework to the schematic version of the circuit from an earlier version of the board.

TRUDGING ALONG BEEPING EVERY PIN TO ITS OTHER END(S)

After another two hours I had the rest of schematic page 2 verified. Perhaps I am speeding up a bit, based on a new method where I first extract all the tests from the schematic as a list of connections; a made-up example would be U4A 4 - U2A 2 - U5E 10- R22. When I had a full page of connections listed, I could swing through with the continuity tester and check off each as it passed. Thus I projected that my average speed for the remaining four would be 3 hours per page.

After only another hour I had page 1 complete - quite a speedup. Page 3 went a bit slower but by the time I reached the end of that page, without having found any broken traces, my confidence in the basic integrity of the board had grown substantially. I could still have bad ICs, since I have already found seven of them, but the board continuity is sound. I had a dinner appointment thus work on pages 4 and 5 started the next afternoon.

I wrapped up work on page 5, finding no missing connections to components. It was time to hook this back up and begin checking out the various circuits as I introduced inputs.

ODDBALL MEASUREMENT OF OPEN COLLECTOR INVERTER OUTPUT

One part of the logic that controls the BACKWRAP output signal is an open collector inverter, pulled up to +5V by a 10K resistor, whose output is feeding two AND gate inputs. When I measure the resistance on the inverter output pin U6E 10, I see 5K to up to +5V but the pullup resistor R79 is 10K.

Portion of the BACKWRAP signal circuit

I lifted the pullup resistor from the circuit and measured open circuit. I measured the lifted resistor as 10K. When I soldered it back in place, the measurement on U6E pin 10 went back to 5K ohms. There would be no resistor in the output circuit of U6E but perhaps some interaction with the AND gate inputs is giving me the reading.

THAT 'DOH' MOMENT

Look carefully at the schematic excerpt above, at gate U2J. I read that as 74LS00 and installed one in the board, but in fact the gate is a dual input AND, while the 74LS00 is a dual input NAND. The correct part number is 74LS08N.

After I checked all the other chips I replaced with74LS00, looking at the schematic carefully, I knew that the five such chips I declared bad based on the boolean logic behavior were in fact supposed to be AND gates.

I will remove all five (again) and populate them with the correct chip. To be safe, after the soldering I have to beep out all connections from the 70 pins, but that will be pretty quick compared to the comprehensive scan I just finished.

Seventh chip replaced, testing resumes at a snail's pace

After replacing the bad 74LS05N chip, I repeated the test to verify that the BACKWRAP output signal would float high if hooked to a suitable pull-up resistor, while the machine was in the idle (REST) state. That did not happen, and it appeared to be the fault of the the same gate. It had a low input, open collector inverter gate with a pullup resistor on the output. This should result in a high output.

Suspiciously, the resistance from the output pin to +5V was measured as 5K but the resistor is marked 10K. This leads me to think that a trace is shorted to some other trace with a 10K resistor as well, producing the reading I found. If the other trace is another open collector output that is pulled to ground, it would match the behavior I saw.

I have been testing connectivity to every pin as I solder in the replacement chips, but that won't show me shorts to additional traces. I will have to find it by trial and error, coupled with hints from the schematics such as OC gates with 10K pullup resistors.

The board has 90 chips, quite a few capacitors and so forth, plus a ton of resistors. The location of the resistor on the PCB is almost random, often nowhere near the chips it is connected to. Further, the numbers hop around randomly by location. It forces me to carefully search the board for each resistor I want to locate, wasting significant time.

To make this easier, I decided to use a high res picture of the board in order to build a spreadsheet for all the components. The chips are labeled strictly by their physical location on the board, but nothing else is so conveniently numbered. The chip rows are numbered 1 to 6 and the columns are labeled A through J.

Therefore I will apply that location scheme to my spreadsheet. Parts below row 1 of the chips are in component row 1, parts between rows 1 and 2 are in component row 2, and component row 7 is for parts above the top row of chips. When a part is to the side of a column letter, I will use the letter to the left of the part. Any part to the left of the J column will be marked as component row K.

My first pass looked at components on the board, placing them in their site by the scheme above. The second pass covered the five pages of the schematic, identifying each component with its page number and approximate spot on the page. I used a Left-Center-Right and Top-Middle-Bottom grid for the schematic locations.

I was left with a few components I could see on the board but not on the schematic. Other components were drawn on the schematic but no visible on the board. I suspect a version mismatch between the board and the schematic. The first signal I traced out which had components on the schematic but not on the board was an input line that had a series resistor and capacitor to ground, intended as a debouncer, but beeping the circuit showed that the input line went directly to the gate. Thus, I will have to contend with the documentation mismatch.

I began a very tedious process of beeping out all the connections between the chips and to the input/output pads. With 90 chips having an average of 14 pins, plus a couple hundred non-chip components on the board, there was a lot of testing to complete. In many cases, one of the pins is fed or leads to a part on a different schematic page, so flipping and recording of source/destination is necessary.

I began randomly with schematic page 2. I realized that once I had tested all the off-page connections from this page, they were tested whenever a signal ran from another page back to 2. This will speed up my page flipping as I advance through more completed pages.

More discrepancies between the schematic and the board arose. For example, when the loading state machine enters the Wrap state, a timer was triggered that on the schematic had a 15K resistor and 100uf capacitor, but on the board I found a 470K resistor and 2.8 uf capacitor. Those combinations are about the same RC constant although with very different currents during charging.

It took me about two hours to complete 1/3 of a schematic page, thus a linear extrapolation would put the remainder of the task at 28 hours work. Some of the pages are sparser and there will be the speedup effect dealing with off-page connections to pages I have already completed, but a conservative estimate is another 2 or 3 days elapsed time.