Dealing with power supply breaker trips in IBM 1130 6V regulator

BACK AFTER EXTENDED TIME AWAY

My wife planned a big party for my 75th birthday that involved significant planning and setup in advance. Just prior I was down with a long viral infection - not flu nor covid, just a mystery ailment circulating in the area - then a nasty cold struck right afterwards. Add in quite a few other obligations and visits and the result was a long period when I was away from the workshop. Happily I am now back.

SPURIOUS CB TRIPS IN 6V REGULATOR

For some time the 1130 would trip the breaker on the 6V regulator when powering back on after the machine had been off for short periods. I also saw some random shutdowns while operating. I had found a weak circuit breaker and replaced it previously, but the issues did not go completely away.

A power supply in the 1130 takes the input mains voltage and produces unregulated DC (nominally 13V) from a halfwave rectifier that is then routed to the regulator module which outputs a well regulated 6V to power the SLT logic in the machine. The regulator module has a circuit breaker that protects it from shorts on the 6V rail but also has an over-voltage protection circuit. 

If the voltage goes too far above 6V, this will fire a silicon controlled rectifier (SCR) to put a dead short across the output of the regulator, forcing the breaker to trip. The SCR fires in tens of microseconds, limiting energy delivered to SLT circuitry in an overvoltage situation. The circuit breaker can shut off in a more leisurely timeframe since the output is clamped to zero. 

The regulator module has two SMS cards plugged into it, one that does the regulation and the other that provides the overvoltage protection. 

CHECKING FOR EXCESSIVE CURRENT DRAW

I placed a voltage and current meter on the inputs to the regulator - the unregulated DC coming from the power supply - to see whether the draw was close to the limit of the circuit breaker. If it was operating near its trip point, it might be susceptible to tripping on the power up surge. The 6V regulator is designed for up to 24A supply, but when I monitored the operation it never reached 7A, thus I believe the output of the regulator is safely below the rated capacity. 

One issue I observe is that the unregulated DC input voltage is just over 15V, but the filter capacitors in the power supply for this input have a 15V rating. Further, the documentation lists the nominal value to be 12V, with the actual about 32% above that. 

The power supply has a wiring diagram to support 115, 208 or 230V input power. My workshop is set up for 230V and the wiring is set for that voltage. I have noticed that the unregulated 48V and 12V rails are also running hot by about 10%. Those two are fed from a different transformer that was also wired for 230V. 

The higher input voltage means that the power supply would have to drop more power to achieve a 6V output, however the current is still well below the capacity of the regulator. I am mildly concerned that the voltage is above the capacitor rating. There is some safety margin, but I might want to replace the two filter capacitors with ones with a higher rating. 

The only mechanism I can imagine for the over-voltage from the power supply is if the primary windings have some turns shorted together, so that the turns ratio increases to drive up the secondary voltage. It would require about 20% of the windings to be bypassed to produce the observed voltage. 

The home for this system once I am done with the restoration is in a facility with 208V mains, thus if I leave the wiring as it is, the voltages will be lowered. Nothing I can do in my workshop, however, except to replace the transformer which would be wasteful. 

The transformer has two primary windings that are either put in series or parallel to support the 115, 208 or 230V line voltage. For 208, the jumper you can see from 1 to 5 above would instead be connected between 1 and 4 on TB-1. That reduces the number of windings however since we appear to have too few windings as is, I would leave the jumper at 1 to 5. 

TESTING OVERVOLTAGE SMS CARD

I pulled the SMS card and hooked it to a bench power supply with overcurrent protection. The strategy was to run up the voltage past 6V until I observed the card clamp the output to a short. The card has a 150A SCR acting as the final clamp, although I set my bench supply to trip out at a much lower current. 

The card clamped the voltage at 6.5V, which seemed like a reasonable setting to protect the circuitry and is well above the adjustment of the regulator at just over 6. Since this may be triggering a bit aggressively I altered the potentiometer to increase the voltage where it would fire. 

In comparison the card for the 3V regulator clamps at 3.4V. The same percentage over for the 6V supply would be a trip point at around 6.8V. That is what I set. 

The problem continued. Whatever causes the breaker to trip occurs even with this higher set point. Thus we have a few possibilities left to chase down:

1. Component issues or drifted values on the SLT regulator card cause it to produce a voltage spike above 6.8V as it is powered up with only a short period of downtime (a few minutes or less). 
2. Some component in the SLT logic downstream from the regulator will short when power returns after a short period of downtime but does NOT short in steady use and clears itself after a few minutes waiting before the next power up attempt.
3. Some component on the regulator has an intermittent connection that is opened by the heating of the parts, which works properly when powered but surges on a repower after a brief downtime. 
4. Some defect in the unregulated power supply produces a surge on a repower after a brief downtime that somehow overwhelms the regulator briefly.
5. The replacement circuit breaker I bought on eBay has the same defect as the original part in the regulator, where it heats up inside the breaker during use and makes it susceptible to tripping during a repower. 

TESTING COMPONENTS ON REGULATOR BOARD AND REPLACING DRIFTED PARTS

I began pulling resistors and capacitors from the SMS board and testing them. I found a few that had drifted too far from their nominal value, which I replaced with new parts. I don't have a source for new-old-stock germanium IBM transistors, but do have some parts available on spare parts boards. Thus I could put each diode and transistor on my curve tracer and validate its behavior then replace any that are bad. 

Germanium transistors often failed due to corrosion either where the lead enters the can or on the actual germanium surface. Silicon forms a protective oxide but germanium does not, thus leaks in the can lead to failures in the transistor behavior. A corroded lead might yield intermittent connectivity as heat causes the can to grow during operation. 

Testing fully assembled new 1130 MRAM board - read retriggering solved!

TESTING FULLY ASSEMBLED BOARD ON TEST BENCH

I put the finished board on the bench and tested it by triggering a read (rising edge of +Storage Read signal) and watching the sense output lines. I wanted to see multiple 1 bits being emitted for a given read, with the output lines pulled down to ground for 80-100ns for all the bit positions that have a 1 value. There should be one pulse for those bit positions and no retriggering causing subsequent pulses every 800 ns after the first one. 

Everything looked good with this testing, so I moved on to the 1130. I frankly didn't do a lot of detailed testing on the testbench because it was cumbersome to move the probes around. For example, I didn't try writes nor changing the address bits to verify that different locations preserved their contents independently. 

TESTING FULLY ASSEMBLED BOARD ON 1130

The PCB was connected to the 1130 system and everything was powered up. I used the rotary mode control to set the machine to Display mode, where each push of the Prog Start button will drive a storage cycle - a read followed by a write. That will raise the +Storage Read line at first which is what will allow me to watch the sense output pulses. 

Having first set the mode switch to Load mode, I loaded memory with various values then turned to Display mode. I want to watch the output pulses on selected bit positions, seeing only a single pulse not spuriously retriggered pulses. I also wanted the value latched into the Storage Buffer Register (SBR) to match what I had stored. 

Instead I saw somewhat random bits showing up in the SBR and the scope pattern for the sense output pulses didn't make sense. I was seeing two 80-100 ns pulses, one shortly after +Storage Read went high and then another at the proper time. I didn't see that occurring on the testbench.

FOUND BAD CONNECTION ON WRITE TIMER CHIP

I realized that in most cases, the same data patterns came out for various addresses as I did Display operations. I was not able to store any different data patterns into RAM, but it was returning deterministically (to at least a superficial level of testing). I then discovered a pin on the write timer chain (first of two timer chips) that was not soldered reliably to the pad. After correction, I could write patterns into RAM. 

ORIGINAL RETRIGGERING ISSUE FIXED

I was not seeing any spurious retriggering beyond the duration of the read portion (1.8 uS) of a storage access, which means that the original bedeviling problem has been mastered. It was kind of a stab in the dark to add in the separate transistors to drive the sense output pulses instead of using the open collector logic gate that produced the pulse. 

I then had a eureka moment when seeing the pulses occurring very soon after the start of the +Storage Read high signal. I noticed that a second pulse at the correct time was happening whenever the board was returning  a 1 bit in that position, while the first pulse seemed unrelated. 

EUREKA MOMENT

Realization rolled over me at that moment. I realized that my sense output pulse, which is a transistor pulling a line down to ground for 80=100 nanoseconds, wasn't connected only to the flipflop that would turn on for the falling edge. There were multiple gates connected together in what IBM calls a wired-OR. That is all the output wires from the various gates are just shorted together - with each of them acting as an open collector driver - so that any of them could activate the flipflop. It was not only a sense output from core memory that turns on the flipflop.

What I was seeing was other gates hooked to the flipflop creating a setting pulse for some other reason. The various gates that produce pulses to set the Storage Buffer Register bit position to 1 are:

• IO bit is gated to B register (SBR) - peripheral  controller drives this
• I (Instruction Address Register) is gated to B 
• A (Accumulator Register) is gated to B
• Core sense output pulses sets B

I don't know what would produce one of those pulses during the T0 clock phase of the read cycle, where I was seeing the pulse on the 1130 side. The gates above should only operate if the machine is trying to store something in a memory location - the IAR, Accumulator or an IO controller word - which should not be happening here.

My next round of testing will focus on what is causing this T0 gating to the SBR. I don't understand why this would happen during a Display mode storage cycle. Either this is a defect somewhere in the 1130 that needs correction or it is a normal behavior that does not cause problems when IBM core memory is used. 

These pulses are pulling the input of the flipflop called the "AC trigger" down to ground, discharging a capacitor that was charged up by the enabling line to the AC trigger. If the capacitor is discharged fast enough and for long enough, the flipflop changes state. It requires about 8ma of current sinking to achieve the setting of the flipflop, times each bit position that has it flipflop set. That is up to 18 flipflops (for a word of all 1 bits).

It appears that something occurring during the discharge was being injected back into the 1130 MRAM board through the supposedly open drain NAND chips. Probably a negative excursion of the line which pulled down the VCC of my board enough to cause the ringing and spurious retriggering. The replacement of the NAND chips with an AND followed by a discrete transistor seemed to resolve this as the transistor could handle the short reverse voltages without any interaction with my VCC and ground planes. 

SOME MANUAL OPERATIONS TESTING THE BOARD

Using the LOAD and DISPLAY modes of the 1130, I was able to put in contents to specific locations and read them back. This is a mode where you take a single storage cycle, pushing the Prog Start button to display or load at the current address. These seemed to be working properly.

I then used the STORAGE LOAD and STORAGE DISPLAY switches on the CE (Customer Engineer) panel to load patterns to all memory locations in a loop or to loop through reading all memory locations. Storing a value of x0000 worked correctly, always returning zeroes. However, when I set the pattern to something else, such as xFFFF, the load appeared to be working but when displaying I got back variable random data and parity errors. 

Since parity is generated on my board based on what is read back from the RAM chip, the only way to see a parity error on the 1130 is if the data being latched into the SBR is not what was read from the chip. This suggests a timing issue or another problem that may be happening during continuous successive storage cycles such as the looping of STORAGE LOAD. 

During my next round of testing, I will examine what is happening during continuous storage cycles and look for defects either in my design, the current board or the 1130.