PERTEC D3422 DRIVE RESTORATION
My error checking state machine is now firing through all its states properly, but it registers a mismatch of the Cyclic Redundancy Check for the header portion of the record. The data field passes muster, oddly. I began digging into the CRC generator logic and its operation, using both the scope for timing information and some diagnostic registers for general debugging.
So far, I have verified that my FSM is presenting the data bits from the disk to the CRC along with a clocking signal. Whether the CRC generator is working correctly is still open. I know that I see nothing shifting out of the output pin, which I believe indicates a flaw in the generator logic.
COMPUTER HISTORY MUSEUM 1401 RESTORATION
I visited the CHM to work on a vexing problem that was rendering one of the two 1401 systems unusable - it has been a few weeks where teams have tried to debug and repair the issue of spurious validity checks when reading in the Hollerith card code for a groupmark (any column with only rows 7 and 8 punched encodes to a groupmark in memory (all bits on in the BCD character).
There are three AND gates that have their outputs wired together to form the validity check trigger condition. Teams have watched the inputs to these gates, finding no periods when any of the three should trigger. Teams have monitored the voltage at the base of the inverter on the gates as that will show which one(s) are activating - but none were shown as activating.
Two of the gates are on card C10 in gate 01B4 while the last gate is part of card E07. using extenders allowed us to disconnect the output of each gate from the C10 card, but the validity checks continued. Since the last AND gate also provides the pullup resistor to keep the line at +6V unless it is triggered, lifting that output from the network also lost the pullup to +6V. This was an impediment to isolating the problem to this card.
When I came in, we first did a check to see if this particular group of AND gates are triggered on the working 1401 system - which they were not - thus we knew that activation of this net on the failing system was a problem.
I installed a pullup resistor on the net so that I could disconnect the output of the AND gate on E07, allowing the net to work properly. The validity checks continued. I then lifted the two other AND gates from card C10, but even with all three gates disconnected, the net still shot down to -6V to trigger a validity check.
One possibility was that when this net was fed to other gates as inputs - there were three such gates that received this validity check trigger signal - we might have had a bad component such as a shorted diode that was feeding some other signal back to our net so that it appeared to be activating.
Another possibility is additional gates driving this net, in spite of the ALD diagrams that show only the three unless a Punch-Feed-Read feature is installed. We don't have the feature and don't even have ALD sections for that circuitry.
At this point, having noticed that the output pin for the AND gate on card E07 had a slip-on connector pushed onto the backplane pin for the output (pin N), we thought to remove this connector. The validity check went away! The connector was pulling the line down when it saw a group mark (but not other valid character codes).
At this point, we powered down the machine and began tracing the net and other signals. We verified that the net in question had all its proper connections, according to the ALD page, without the slide-on connector attached. That is, we had all three AND gate outputs connected together and those connected to the three gate inputs that the signal should drive.
We began tracing the slide-on connector wire and discovered it left gate 01B4 and snaked through the machine to gate 01B7 on the back side. We verified continuity to the wire to a paddle card connector plugged into E04 slot of that gate, on pin C. It was extremely difficult to follow the wire on the backplane, which was a formidable mass of wirewrap connections and wires, but eventually we traced it to A16 pin N.
That should have given us the ALD page where this slot is used, so that we could figure out what this signal was used for. It became the working assumption that the slide-on connector belongs somewhere else on gate 01B4 but someone pulled it off its proper location and stuck it back in error on card E07. If we could find out what the wire actually carries, we could find where to attach it.
Alas, the slot A16 is described as reserved for RPQ, meaning it was an undocumented modification to the machine. This is bad - the documentation of the 1401 system does not match what we have. At this point, we know that the mystery wire is the output of an AND gate stuck in A16, without a pullup to +6V. We know this because the line sits at ground unless it is pulled down to -6V when activating. It is supposed to be connected to some net where another gate furnishes the pullup.
Some punch side problems exist and are getting worse on the same machine. We ran out of time to chase those down - this is volunteer work done with a few spare hours - but the team will work on this on Wednesday.
To resolve the mystery wire may require tracing out the RPQ circuitry and finding out what it is doing and where it is connected. For example, the wire connects to the AND gate output pin N, which is one of two AND gates on the card. We can look at the input signals for that AND gate to see where those come from. Laboriously, this could be built back into the missing ALD diagram or corrections to our ALDs.
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