Digging into why card data isn't being returned

 TACKING WIRES TO USE WITH SCOPE AND LOGIC ANALYZER

I tacked on small wires to the legs of ICs at strategic points in the generation of the impulses that trigger our microcontroller to latch in the contents of each card column. I began with the earliest precursor signals, monitored the control flipflop, then looked at various gates on the way to the external interface wires. This allowed me to put the board into the reader but have access to the various signals.

EVALUATING THE IM GENERATING LOGIC

Once a pick takes place, recognition of the first dark edge means the card has entered the photocell region. This resets the column counter and does some other timing to establish the time when the counter is advanced to represent the arrival of the next column. 

The counter produces signals such as 0CR (left edge), 81CR (arrival at column to the right of the last data containing position on the card), 84CR (when the trailing edge should have passed resulting in light on all photocells, and 84 (a delayed end of card counter used only in certain models of the reader).

At the time of 0CR generation, the Impulse Marker control flipflop is turned on, which generates the timing pulses for each column that will produce the IM on the interface. Our microcontroller sees the IM and latches in the 12 card row values for that column. This occurs 80 times to fill a one card buffer in our controller. 

The signals for columns arriving are tied to a coil reacting to teeth on a spinning wheel in the card feed mechanisms. Those pulses are timed and a precise delay is counted between the last tooth being detected and the exact time that the first photocell goes dark from the leading edge of the card in motion. This delay is applied to each subsequent set of pulses to synchronize timing pulses to the position of the card. That is, we would receive two more pulses, add back in the counted delay, then send out a gated version of the phase C and phase D clocks at that time. These gated clocks, called ST0C and ST0D, are used to latch and clear the photocell contents, to advance the column counter, and to emit the IM pulse.

As you can see from the description above, quite a bit has to happen correctly in order to have our IM pulses produced and the reader be happy with the reading process. At certain column times, e.g. column 81, there must be no light detected on any row. At other times, e.g. before column 0 and at column 84 time, there must be light on all twelve detectors. This is a kind of check that verifies that the card moved at the proper speed through the reading station. We get an error if these checks aren't successful.

RESULTS MONITORING THE LINES I TACKED TO THE BOARD

My wires were tacked on different pins on the PCBs to observe various parts of this process. I had to see the timed pulses going through, the card position signals such as 0CR and 81CR get produced, the IM control flipflop be set, the IM pulses be generated, etc. 

I did catch a single IM but most of the signals never occur. The issues are earlier than where I was looking. It was too tedious and cumbersome to tack on many wires, label them and try to hop between them with a scope. I decided I need to wire the logic analyzer to the backplane, look at all 34 signals that are available there, and draw conclusions from the mass of data before I try to narrow in to individual ICs or small circuits. Each of the four PCBs has over 30 chips mounted, making the scattershot method impractical.

PREPARING BACKPLANE SIGNAL CONNECTIONS

The backplane is a PCB that runs between the six connector positions for the right side of the card cage. The PCBs have a 2x18 connector that fits into the backplane; in addition there is a second 2x18 connector on the left of the card, with discrete signals relevant to the specific PCB rather than signals shared among all. 

There is not enough room between the connector and the backplane PCB to snag signals with any hooks. However, since the machine has six slots but only four cards fitted, there are extra connector positions on the backplane that do NOT have a connector soldered down. This gives me 36 holes that I can attach wires to, bringing the 34 signals, VCC and ground out where I can hook to them.

I carefully soldered on the 34 wires, preparing a means to wire up the logic analyzer and scope more effectively. The logic analyzer needs a good clock to latch in signal values, but the backplane provdies only four 120KHz clock phases (A to D). Those phases are developed out of a 480Hz signal on the Clock card, so I tacked on one wire to bring that master clock out to drive the logic analyzer.

As a quick check, I used the logic analyzer to capture the four clock phases and used the scope to observe all the clock signals. Everything was good, so I am comfortable that after I wired up the other 30 signals I can capture meaningful clues about the machine problems. 

capturing clock phases A thru D

It was then the end of the workday, where I saved the configuration and shut it all down for the evening. Tomorrow I will continue with the wiring and analyzer setup.