Resolved OneDark signal issues, moving forward with diagnosis of M1000 card reader

 REPLACED INVERTER CHIP TO RESOLVE THE INVALID VOLTAGE LEVEL

I unsoldered some chips that are tied to the OneDark signal, which had been floating at an invalid 1.65V level erratically. With replacements installed, the signal is now behaving properly. That was a vexing issue as the problem would sometimes disappear only to show up randomly at a later point.

Desoldering chips with the Hakko

I set up two VOMs to monitor the input and output pin of the driving inverter and had really great voltage levels. Using a zip tie to obscure light in the photocell channel made the two signals reverse voltages, exactly as they should.

Left is the wired-OR, right is the OneDark output

Blocking some photocells to trigger OneDark signal

VERIFIED THAT ST0B SIGNAL ISSUE IS FIXED

Having replaced a NAND gate that was driving the wrong output signal based on its input signal values, I suspected that the ST0B signal would now sit properly at logic high when not active and pulse on when gated. I was able to verify this with the scope today.

ST0B signal produced

EXTENDER CARDS DISAPPEARED INTO THE USPS BLACK HOLE

I sure could use the extender cards coming from Datamuseum in Denmark, as there are so many issues that require probing of the components on PCBs while they are stacked in the card cage. I have had to tack on wires, reinsert, test the levels and repeat as I chase down faults. If the card were extended I could just touch probes or attach leads. 

Tacking wires to monitor signals on pins

The boards arrived into the USPS international shipping center in Chicago on the 30th, with no trace of them seen since. It is possible they are moving silently through the system and will show up at my doorstep, but more likely they are heaped in a pile in the center waiting for someone to direct them onward. 

CIRCLING AROUND IN THE SYNC CONTROL LOGIC TO FIND NEXT FAILED PART

Currently when I try to read a card, it reaches the point where it should start processing card column positions. It does this by counting down from a preset value that reflects the time the card will travel from first obscuring the photocells until it is centered in the holes that would be punched if there was a column 0. That is, the position that is one column width to the left of the first data column. This should be recognized by the signal 0CR and a check made that no light is detected on any of the twelve row photocells. 

The preset countdown clock is working well in the logic analyzer trace, the zero detector asserts the logic condition ZERO, and I see the first tooth of the wheel producing a pulse. However, it stalls at this point.

What should occur is that a new clock, OSCLK, should begin counting from the OneDark first turning on up until the ZERO occurs. This sets up the offset count. Then, the next time a tooth is detected a third clock, OSUCLK, will count up with a comparator triggering once the new count matches the saved offset count from OSCLK. None of that is happening.

Without the OSUCLK logic, it will never trigger the signal CSDS that says we are at a sampling point for a card column, thus never latch the photocell data, never emit an Index Marker pulse, and never increment the column count. The entire card cycle ends when the column count reaches 84 (signal 84CR is produced), but that doesn't happen so we are hung. 

Tomorrow I will move around tacking a small number of wires on likely gates until I find the one(s) that are malfunctioning. Could be a tedious time.