Careful checking and validation for the 1130 Extender project

CHECKING 1130 ALD CONNECTIONS TO 160 PIN SAC CABLE

My schematics for the IBM 1130 - Automated Logic Diagrams or ALDs - shows the pin name on the Storage Access Channel (SAC) connector for every system signal that is sent or received by my extender box. I cross checked the pin assignments from the ALD to the documentation I created that was used for the wiring of my box.

I discovered that two signals I receive are swapped! It appears that nothing I had been doing depended upon those signals, otherwise I would have discovered this earlier. The two signals are CPU Parity Stop and X2. 

When the machine is doing cycle stealing, the process that is called DMA in modern systems, it uses a set of eight clock states called the X-clock, X0 to X7. The SAC feature provides just four of them, X0, X2, X4 and X6, because devices that use cycle stealing need these to know when to assert certain control signals. The eight clock cycles span one core memory access cycle - the first four are during the destructive read of the location and the second four are during the write-back or update of the location. 

I will switch these so that my FPGA sees the proper signals. I would have spotted this when the red LED on the box began to flicker on and off during any cycle steal operations, since that LED is assigned to the CPU Parity Stop error signal. 

CHECKING 160 PIN SAC CONNECTOR CONNECTIONS TO RECEIVE/SEND CIRCUITS

I then beeped out each pin on the SAC connector to verify that its wire is properly labeled. That will be important to get them attached to the correct receive or send circuit. Too, the nature of each connection, whether send or receive, has to match the type of circuit on my new board.