Halfway through entering signals into IBM 1130 database

REACHED HALFWAY POINT, 113 ALD PAGES ENTERED

I am partway into volume 3 of 4 of the Automated Logic Diagrams, having reached page 18 of this volume which is the 113th page I have entered into the database. For each I entered the gate, compartment, card slot and pin number along with the ALD page/gate and signal name. 

The memory control pages were particularly slow and cumbersome to enter, because I had to deal with the challenges of three different memory configurations. These were handled by notes on the pages about jumpers to place in various situations. I had to convert these to a form of signal name and record the pin locations.

The basic memory building block is an 8K core stack that fits on a backplane with surrounding SLT cards as drivers and other control logic. The smallest machine model is 4K which is a cut down version of the 8K stack. The stack logically consists of 18 planes, storing a 16 bit word and two parity bits. There are 8192 locations that can be addressed by unique X and Y values that define a point on the plane where one core sits. 

Larger machines than 8K can't fit in the standard part of the frame and instead require an additional cabinet extension, called the blister, which fits on the left side of the machine. This has one or two additional gates so that it can hold up to 32K of core. IBM calls machines with the blister Expanded Storage models. 

Because the signal distances are longer, it required line drivers and terminators, adding some gates and circuitry. Thus, there are jumpers shown on the ALDs to route signals to or around those driver gates (whose cards would not be populated on a non-ES machine). 

In addition to the ES configuration, later models of the 1130 were enhanced with higher performance. This was accomplished in part by fitting a different core storage module that was faster. The original models have a 3.6 microsecond memory cycle time, using the 'SJ-4' core storage modules. The faster models operate with a 2.2 microsecond memory cycle time using the 'SJ-2' core modules. 

There are additional gates for signals to 'look ahead' to provide conditions early enough to fit the tighter timing in a faster machine. A particular chain of logic gates might work just fine with the 450 nanosecond cycle time but it has enough serial gate delays in the chain that the 275 nanosecond cycle time is not long enough. 

Providing an early signal reduces delays in the chain and ensures reliable operation for the faster models. There are notes in ALD pages and jumpers that reflect where the design would differ between the two machine speeds. 

I was able to record the data so that I can debug machines like my own that are expanded storage models, as well as smaller machines such as the one I am currently restoring. I will be able to debug the 2.2 microsecond models if I were to work on one as well as the 3.6 us models I have worked with. 

All these variants and jumpers made the database entry particularly slow for the memory pages. Fortunately it was compensated for by the major register pages. These are replicated circuits - one SLT card provides the circuits for 2 bits of a word, thus eight of them are needed to produce a full 16 bit word register. 

In fact, these cards usually implement more than one register at a time, so that the RAxxx pages implement two bits of both the A and the U registers in one card. The RBxxx pages implement three registers, two bits at a time for each on one card. In a bit of inside humor, these registers are the I, B and M registers and the pages are labeled in that order to spell out IBM. 

Because of the high degree of regularity, I could copy and paste, change labels, change the particular card slot number and then handle the small variations that come from the routing over cables between backplanes. This sped up the entry of these pages quite a bit.