Feeling good about generating a read head stream of pulses but not done yet

IMPROVED FAKE MEMORY MODULE TO SEQUENCE VARIOUS DATA WORDS

I made changes to the fake memory module such that it would produce a known stream of word values that appear to be the data read out of RAM. Eight values were chosen with an eye to validate that words are produced correctly and that the first and last bits of adjacent words are not corrupted due to poor timing of the read results.

TIMING IMPROVED TO ENSURE THE NEXT RAM VALUE IS FETCHED BEFORE EACH WORD

I had to find a way to trigger the read of RAM late in the bit generation of a word in order to have the data available for the next word to start its output. Since the last four bit cells are a check word whose value is already calculated after finishing the 16th data bit, I could issue the trigger at this point with no consequence for when the RAM result is latched in. 

That new value from RAM can appear anytime from the start of the first check bit all the way to the beginning of the first data bit of the next word. The first value from RAM has to appear before word 0 starts its generation, thus I found a time during the latter part of the sync word output where I could trigger the read. Since sync is a fixed pattern, it does not matter when the RAM data arrives as long as it is by the time word 0 begins. 

CLOSE STUDY OF BIT GENERATION DONE

To assist with this study, I emitted a pulse at the start of each bit cell, which should neatly delineate the pulse or pulse pair that are a 0 or a 1 value. It also allows me to visually look for incorrect duration of bit cells. Coupling this with the edges when the word number changes and I had all the tools I needed to verify that my circuit was operating as intended.

I did find a number of suboptimal situations which I am working through. Adjusting here and there. Hopefully I will be happy tomorrow and ready to move on to capturing sector writes.