Simulating getdata and getcommands modules complete

GETDATA  AND GETCOMMANDS SIMULATION

I completed simulation and verification of these two modules, using a testbench that toggled signals as the H2F and H2F LW bridges are expected to operate. The signals looked clean and my error state detection operated as I expected. 

MODULE DEVELOPMENT FOR LOGIC TO DRIVE THE LOAD AND UNLOAD PROCESS

This next higher level module will be called when the getcommands bridge receives a command from the Linux side requesting a load or unload. It will then loop to move an entire virtual 2315 cartridge image between the Linux side and the dedicated 1MB of SDRAM we control from our FPGA side. 

For load, it will wait for the Linux side to send each group of four words from the file selected by the user, then write that group out to the SDRAM in its assigned spot. The Unload operation will fetch each group of four words from SDRAM and then wait for the Linux side to read that group in order to update the file image on the SD Card. 

As I polish up this module's logic, I simulate it with a testbench to watch it appropriate drive the various bridge communications between FPGA and HPS sides of the chip. Rather than just simulating the requests to the various modules I have already tested, I chose to link them together to ensure this works properly all the way down to the Avalon MM interfaces of each bridge.