Continued testing 1130 MRAM board - working on the retriggering

WIRED UP A TIMER TO SEE ACTIVITY ON ALL PINS

I tacked small wires on the pins so that I could watch the various pins to determine where the problem arises that results in the SN74LVC1G123 chip retriggering when it shouldn't. First I watched the VCC and ground rails at the chip to see if they were contributing to the problem, but they were rock solid.

I then focused in on the retriggering and noticed that from time to time, I would get a single pulse but mostly repeats. I zoomed in and looked at what might be different when it didn't retrigger. I saw that the input signal +Storage Read at the output of a NAND gate rose for a very brief time right as the second timer in the chain emitted its short pulse. When the dip was 2V or less, there was no repeat, but if the dip dropped further, the chip fired again. 

Yellow - trigger, green output, purple second timer output

yellow - inverted trigger, blue output, pink RC node

INTRODUCED FILTER TO SWALLOW THE BRIEF DIP

I added an RC network between the +Storage Read signal coming from the cable and the logic circuits that fire the timers and control other devices on my board. The initial filter was set conservatively with a time constant of 4.7ns. 

It was working pretty reliably so I introduced another network between +Storage Write and the logic using that signal on my board. When I tested, a few times I didn't see the timer trigger at all during a write. I also saw the read timer begin to retrigger from time to time. 

Tomorrow I will make the RC time constant bigger to see whether this quenches the retriggers. Will also dig even further into the behavior of the timer chip - both the first read timer and the first write timer - where the retrigger occurs. 

What I noticed is that the retrigger happens on the first of two timers in each chain, but not on the second. That is, the circa 100ns pulse emitted by the second of a chain does NOT retrigger while the circa 800ns first timer output is where the retrigger occurs. This further bolsters the idea that the issue lies in the trigger signal to the first timer. 

Continued testing 1130 MRAM board - dealing with the signal bounce and retriggering

HAD LARGE TRACES FOR 3.3V, GROUND, PLUS GROUND PLANE

I over-engineered the size of the traces to deliver 3.3V around the board as well as deploying a ground power plane. Decoupling capacitors very close to each chip are also a feature of the design. However, if the regulator can't instantaneously deliver enough power when many gates switch, particularly the 8ma sink required for each of sixteen sense bits and two check bits, then it could cause the sags and anomalies I was observing. I had what I believed was adequate buffering already, but I tried to bump it up.

BUFFER CAPACITOR ADDED

I tacked on a 470uF capacitor across the 3.3V and ground rails to give the board a bigger buffer for energy delivery. The final design would have an SMD version placed neatly on the board, but this is a rework of my current PCB thus I added a through hole part. 

No change when I tested. The +Storage Read signal had a glitch in the middle just when the first read timer ended and the second timer started its pulse. The first timer immediately retriggered. When the word being read had many bits that were one, the retriggering would continue for many more cycles, but when the data word was all zeros I only saw one retrigger. 

BYPASSING THE LOW SIDE MOSFET

The next theory was that my decision to use a MOSFET to isolate the 1130 ground from my board when not powered was introducing a problem. I jumpered around the MOSFET so that the ground was direct, yet the issues remained. The signal was slightly less bouncy but still enough to retrigger. 

ADDED TERMINATION FOR THE SIGNAL

The signal looked relatively clean except for the glitch at the time the second timer was emitting its pulse. With 74HC series chips there is generally no need to do impedance matching, particularly with relatively slow signals as in the IBM 1130. However, the cables that IBM uses with Solid Logic Technology (SLT) machines such as the 1130 are designed with 95 ohm impedance. 

I matched the impedance of the signal to see if that would clean up the signal, but it made no difference. So far I have been trying everything I can think of to stop the bad behavior.  Reading out a word of 0xFFFF will fire off eighteen sense bits (the word plus two check bits) thus sinking about 150ma over 100 nanoseconds. 

WATCHED THE +STORAGE READ SIGNAL AT ITS SOURCE

I put a scope trace on the source gate that generates the +Storage Read signal, before it ran across one backplane and over a cable to a different card compartment and then over cable T3 to my board. The signal looked the same at the source. I find that suspicious. Next time I am in the workshop I will remove the PCB entirely and watch the signal at the source again. If the glitch is coming from the 1130, I would have to address the problem differently than if it is a weakness on my board. 

Side project - MV864A meter restoration - almost complete schematic produced

FINISHED THE RANGE ATTENUATOR WIRING AND PART NUMBERING

The numbers for the resistors were completely changed from the version in the manual, but they were mostly in the same arrangement. The values were changed a bit, with my version using standard resistance values while the newer version in the schematic took advantage of more diversity in values available later on. 

ONE MAJOR QUESTION REMAINS TO BE ANSWERED

The version in the manual uses a constant current source produced by a transistor in the power supply to develop a voltage drop across resistors being tested by the meter. I don't know where my version gets the voltage to deliver to the resistors under test, as I don't see zener diodes, transistors or other parts that would act as a constant current source. I will have to trace out the wire from the function switch section C wiper as that is where the supply for resistance testing is delivered. 

THE SCHEMATIC IS ESSENTIALLY COMPLETE EXCEPT FOR THE QUESTION ABOVE

I HAVE WHAT I NEED TO TEST, RESTORE AND  CALIBRATE

Since I know the circuit design, parts numbers and test points for my version, I can use the calibration and diagnostic methods from the manual to get this meter in perfect shape. 

Continuing testing of the 1130 MRAM board

REWORK DONE TO THE BOARD AND REINSTALLATION ON THE 1130 FOR FIRST TESTS

I lifted pins, added jumpers and wires, to resolve the design flaw I had discovered. The repaired board was put back on the IBM 1130. I then did some Load and Display tests with the logic analyzer connected to validate the behavior for these simple cases. 

It was still producing spurious sense bit outputs. I switched to the oscilloscope for an analog view of the signals. The spec sheet for the SN74LVC1G123 timer chip indicates that a logic low is 0.8V or lower and logic high must be 2V or higher. The unasserted state of the +Storage Read signal is around .2V and it sits around 3V when active. 

However, I can still see retriggering of the timer. The yellow trace is the +Storage Read signal, the green signal is the first time which delays about 800ns and the purple signal is the second timer which produces an 100-120ns pulse. The pulse is what generates the -Sense Bit X outputs. 

I can see the first timer immediately retrigger around the middle of the trace, thus the second timer produces more than one pulse. There is some funniness on the +Storage Read signal right as the second timer fires, which dips down low enough to look like a logic low. Thus as it recovers, the first timer fires anew. 

As a clue, when the word being read is all zeroes, the pattern above occurs. Just two pulses (one more than desired). However, when the word is mostly ones, the retriggering seems to continue long after +Storage Read goes back to low. 

I have to mull over how this might be occurring. I did fix the vulnerability where a machine cycle shouldn't send out sense pulses because +Storage Use is low. Whatever is happening here is not that condition. 

This may be an issue with inadequate ground conductance causing some bounce in the levels when many gates are switching, or perhaps I need to bump up the capacitor at the output of the 3.3V voltage regulator. 

Side project - MV864a meter restoration - simulations and look at the non-board wiring

SIMULATED PREAMPLIFIER AND DRIVER OUTPUT SECTIONS

The photoisolator component has twin photoresistors that are driven by two LEDs. The LEDS oscillate at 94Hz, thus the resistors should pick up the 94Hz signal, with the input to the meter driving the photoresistors. 

The current flowing through the photoresistors is detected by a MOSFET and a string of amplification stages, giving the 94Hz signal at an amplitude based on the input voltage. That is then further amplified by the driver output circuit. The signal from the driver output circuit is rectified to turn a positive and negative cyclic signal into a stream of positive pulses. 

The positive pulses are mixed with the original 94Hz source in the synchronous demodulator to recreate a DC voltage that is an analog to the original input signal. This also detects whether the input was negative or positive and causes the output of the demodulator to take the same polarity. 

LTspice does not have a photoresistor model. In addition, I had to model the effect of the LEDs producing the 94Hz alternating positive and negative square wave. Since I have no specs for the LEDs, photoresistors nor the MOSFET detector, I had to guess a bit to produce a reasonable result from the circuit. 

I used a voltage source to generate what the photoresistors would pass into the MOSFET, consistent with a current from the input flowing through them modulated by the change in resistance as the 94Hz light from the LEDs hits them. The circuit simulated properly, thus I believe that everything except the synchronous demodulator checks out. When I simulate that part, I will feel confident in the schematic I captured by the reverse engineering. 

LOOKED AT DISCRETE CONNECTIONS ON THE METER

I began to trace out the wires coming from the main and power supply boards. For each wire, I noted the color and its destination. As I did this, I looked closer at the Range Attenuator and Function switches. My working assumption was that the range attenuation and function switching wouldn't have changed more than trivially between the version I have and the schematic shown in the manual. To my dismay I discovered the differences are more substantial.

CHANGES IN THE ROTARY SWITCHES FROM MY VERSION TO THE MANUAL VERSION

The Range Attenuator switch in the manual has eleven sections of 15 positions, but the meter I own has only nine sections. The Function switch has 7 sections, just like in the manual, and it matches. I am going to have to dig in and reverse engineer this to see how it has changed. 

The last two sections seem to match between the meter I own and the manual schematic. Wires run to the back panel that has all the calibration potentiometers to adjust each of the fifteen ranges so that the meter produces the correct reading. Other than changes in the component numbering between the versions I believe it is identical. 

Calibration board on right, wires to Range Attenuator switch

I began to label all the components from my photos of the actual meter, so that I know the parts number of each and can apply that to the reverse engineered schematic as I bring the copied over schematic part from the manual into agreement with the actual wiring. 

IBM 1130 MRAM memory board - root cause of the unwanted stream of pulses from the board being corrected

REALIZED THE CAUSE

I had made a tweak which I thought optimized my design, so that the timer pulses that control emitting the sense output bits are triggered by the rising edge of the +Storage Read signal. On the surface that seemed logical, as we only want to fire them off when we are doing the read portion of a storage cycle.

However, the genesis of the +Storage Read signal is when the IBM 1130 is in clock states T4, T5, T6 or T7. This happens on every machine cycle, not just during memory access. Thus, we would trigger the pulse to emit sense bits on the second half of every machine cycle, not just the ones we want. 

The +Storage Use signal is what indicates that a particular machine cycle involves a memory read. Thus, I should have triggered this when both +Storage Read and +Storage Use go high. Originally the design did use this logic, but to save gates I switched to simply using +Storage Read, forgetting that this is not just raised during a read attempt. 

RESOLUTION OPTIONS

There is one spare gate on a 74HC00 chip, a NAND, that I could press into service to make a signal when both +Storage Read and +Storage Use are high. The original design used this gate plus another that inverted the output to produce a positive going pulse as the trigger to the timer chip's notCLR input. I needed another gate for a different change so I made the ill fated decision to drop the +Storage Use from the trigger conditions. 

The solution is to use the spare gate on U14 to produce a low output when both +Storage Read and +Storage Use are high. The timer has three control inputs - ~A, B and ~CLR - which have to be reconnected. There are three ways the timer can be triggered - 

1. a rising edge on ~CLR while ~A and B are L and H
2. a rising edge on B while ~CLR and ~A are H and L
3. a falling edge on ~A while B and ~CLR are H and H

 The original design used option 1 but I only have a falling edge from the added NAND gate, so I have to shift to option 3. Thus those three control pins have to be rewired (actually only ~A and ~CLR but for technical reasons I change all three. 

Of course I could redo the board, waiting a couple of weeks for parts and the new PCB, but that is punishing. I instead looked for ways I could rework the existing board to function as intended. I did figure out a way to rework the board. 

It involves lifting six pins total from two chips to disconnect them from the existing board traces. Mainly this is due to traces running underneath the chip not just off to the sides, so that cutting traces would be more of a challenge. I then add some jumper wires across pins and over to the +Storage Read pin (cable T3 pin lower 6). 

REWORK STEPS

I have to lift pins 5, 12 and 13 from chip U14 (the quad NAND device) and pins 1, 2 and 3 from chip U5, the timer device. This isolates the pins from the existing connections on the board traces they had been soldered to. 

I then put short jumper wires between U14 pins 1 and 13, as well as 5 and 14. I then add a wire from U14 pin 11 (output of our NAND gate) to U5 pin 1.  On chip U5 I add short jumper wires from pin 8 to pins 2 and 3. Lastly, I run a wire from U14 pin 12 and the connector for cable T3, on the lower position 6 (+Storage Read). 

The schematic version of the rework is to disconnect the +3.3V connections to chip U14 pins 12 and 13, the previously unused gate. Wires run from these pins to cable T3 lower 6 (+Storage Read) and to U14 pin 1 where the +Storage Use signal is connected. 

Over at the existing connections to chip U5, we disconnect the three existing control signal connections.

Jumpers tie pins 2 and 3 to +3.3V while we run a wire from U5 pin 1 over to U14 pin 11 where our new control signal is generated. 

GOOD VERSION OF SCHEMATIC AND PCB LAYOUT

IBM 1130 MRAM memory replacement - investigating Parity Check and random data occurrences

LOGIC ANALYZER CAPTURE RESULTS

I hooked up the DSLogic analyzer to the 1130 to capture key signals allowing me to figure out what is going wrong with the read and write process and the phantom parity check issues. The device can sample up to 16 lines at a time, which is not enough for a full capture of every signal of interest, but should allow me to watch subsets until I spot an issue that hints at where to zoom in. 

If I had unlimited channels, I would capture:

• all 16 B reg values. 
• all 16 sense bit outputs
• check bit 1 and 2 sense outputs
• storage read and storage write commands
• T0 to T7 clock pulses of the 1130
• parity check detection signal
• all 13 SAR values going into the board

I began with sampling  some timing related information to see if I am doing things at the wrong time. I grabbed storage read, storage write, T0, T2, T4, T6, the parity check signal and some sense bit outputs including the check bits. If the sense bits are being produced at the wrong times, e.g. too late in the read cycle when we are already starting the write, then it might lead to the conditions I am observing. 

Doing a read of a word that is all zeros produces the correct data without a parity check, but when the word has bits that are a one, I saw that the board then was emitting a continuing stream of bits long after the read was completed. 

FAILURE MECHANISM

The circuitry for the B register will set the bit to one if a pulse arrives on the sense bit lines - any time that it arrives. It is not gated to only activate during the time of a read, it will flip on the bit whenever it arrives. Thus if my board emits sense pulses it is going to stomp on the B register. 

Why this is happening was not immediately obvious. I put a timer chip on a breadboard and tried to cause it to fire off a stream of pulses but couldn't create a plausible sequence to make this happen. The chip I am using on the board, sn74lvc1g123, is a retriggerable timer, thus it can produce a stream of repeating pulses in the correct circumstances. 

I will have to do some analog investigation, as the issue might be noise, invalid logic levels or other issues that won't show up on the logic analyzer.