1130 MRAM - quick check after removing large buffer capacitors

PREVIOUSLY ADDED CAPACITORS WHEN SUPPLY SAG SUSPECTED

A while back I worried that the rails on the PCB were sagging during the heavy output pulses from the eighteen sense amplifier pulse generating gates. The design I originally used, informed by the datasheet for the LDL1117 voltage regulator, was a 4.7 uF capacitor across the regulator 3.3V output, as well as .1uF decoupling capacitors at every chip.

I tacked on a 470 uF capacitor to provide substantial additional buffering, but the spurious retriggering of the timer chips continued to occur. At my last session, I added an additional 46,000 uF across the 470uF and 4.7uF capacitors. The symptoms continued. 

POSSIBILITY THAT EXCESSIVELY LARGE CAPACITANCE LEADS TO SUPPLY OSCILLATION

However, it is a known issue with switching regulators that too much buffer capacitance can lead to the regulator oscillating on momentary demands because it is too slow to notice the energy being pulled from the capacitor, then has difficulties recharging the energy into the capacitor. 

While the LDL1117 is not a switching device, instead it is a linear regulator, which is why I initially disregarded the risk of excess buffer capacitance. However, it regulates with an op amp and oscillation is certainly possible if I have imbalanced the chip too much. 

REMOVED BOTH EXTRA BUFFER CAPACITORS AND RECHECKED 3.3V AND GROUND

I de-soldered the two capacitors from the PCB, reverting to the recommended 4.7uF capacitor across the output of the regulator chip. I then used the same measurements with the oscilloscope that I had yesterday, looking at AC variations on the 3.3V output of the regulator and also between the ground on the PCB and the ground out at an SLT slot on gate B compartment A1 of the 1130 system. 

RESULTS OF RECHECKING

The 3.3V rail is much more stable with the extra capacitors out of the circuit. Unfortunately I still have the spurious retriggering. 

What is still happening is a big bounce between ground on the regulator of the PCB and the ground pin of an SLT slot in the 1130. 

ADDED A SECOND GROUND WIRE FROM THE 1130 TO THE PCB

The PCB is connected to the IBM 1130 ground terminal block by an 18 gauge stranded wire. That is the same wire type used to connect the grounds on all the SLT backplanes from this terminal block. However, I hooked up a second 18 gauge stranded wire between the ground terminal block and the regulator ground connection. No difference in the observed bounce. 

GROUND BOUNCE TRACE OF 1130 SLOT PIN MAY LIE DUE TO CONNECTION METHOD

I don't have scope probe tips that slide over the .025" pins on the rear of the SLT backplane (official name is SLT board). I have used jumper wires, male-female type, to fit over the SLT pin and have the scope probe hook grab the other end. In other words, I don't have a great low resistance direct connection to the probe. 

GROUND BOUNCE MAY BE DUE TO REGULATOR CONNECTION TO PCB GROUND

The ground plane of the PCB is an inner layer, but the connections are on the top layer. Vias carry the current down to the inner layer. I thought I had plenty to ensure excellent conductivity. Since I have a helper wire from the regulator ground where my new wire attaches all the way to the read timer chip grounds, the retriggering doesn't fully make sense yet. 

OBSERVATIONS

When I combine the images of the ground bounce relative to the 1130 SLT logic with the +Storage Read signal coming into the PCB and the pulse retriggering, the wiggles in the control signal seem directly correlated with the ground bounce as seen at the 1130 SLT board. When the data returned has more one bits, the retriggering pulses continue longer and the ground bounces with them.

A cause appears to be the NAND gates sinking the current from the 1130 side to flip on the bits in the B Register. The 1130 side has a capacitor that is charged up to sensitize it, then when our PCB sinks that to ground, the edge causes the flip flop in the B register to turn on. 

Four feet of 18 gauge stranded wire should drop about 7 millivolts with that current draw, not hundreds of mV. Two parallel such wires should reduce the max bounce further. 

Still not sure of exactly what is causing this thus not certain how to correct it, but getting closer. 

1130MRAM smoking gun found

SCOPE ON 3.3V AND GROUND, TRIGGERED BY THE ANOMALY

I set the scope on the yellow trace and triggered on the first fall of the +Storage Read signal, which will occur during the glitch that surrounds the spurious retriggering in the read timer chain. I wanted to look extremely closely at the 3.3V line at the time of the anomaly, watching very closely for any variation that suggests bouncing on the ground or 3.3V lines that feed all the chips.

I set up the green trace to a wire plugged into a ground pin in gate B compartment A1, in AC mode with 200mV per division sensitivity. The blue trace was hooked to the +3.3V side of a huge capacitor I added to bolster the 3.3V supply stability, also on 200mV per division in AC mode. The purple lead was connected to the output of the second read timer to watch for retriggering and thus duplicate pulses. 

Because I suspected that I might have some bounce in the supply, I had added a 46,000 uF electrolytic in parallel with the 470uF filter capacitor I previously added. Even with all that buffer capacitance I was seeing the retriggering occurring. 

When I looked at the 3.3V output at the buffer capacitor, I saw a horrifying bounce of 800mV up and down. 

Watching the 3.3V supply bounce along with the second read timer output pulse, the correlation is obvious. 

Watching the ground pin on the IBM 1130 to compare its level to the ground at the huge filter capacitor on my board, I saw about a 700mV +/- bounce as well. 

This is a classic analog issue, lying beneath the digital abstractions of logic gates. There is likely some kind of resonance or ringing at play here, looking to be around a 1-2 ns cycle duration. My suspicions are going to be aimed initially at the power traces to all the chips, but I will also look into the chip bypass capacitance values I chose and its interplay with the board and trace capacitance, resistance and inductance. 

I suppose I will also route the traces much more carefully to round every bend and avoid any spots that could produce reflections, since this board designed for 2.5MHz signal rates is having more difficulties that I had anticipated. 

It seems inescapable that I will have to buy another round of PCBs to fix all of this, incurring the cost and delay. 

1130MRAM spurious retrigger - what it can not be then musings

NOT A FAULT OF THE CONTROL SIGNALS

The control signals that fire off the timer chips are +Storage Read and +Storage Write. They are produced by the IBM 1130 using the circuitry below:

Four flipflop outputs T0, T1, T2 and T3 are wired together in a dot-OR configuration, where a pullup resistor (750 ohms to 3V) will produce a high output if none of the four feeding gates are conducting but any one or more of them turning on will pull the shared line down to ground. Thus this is high if none of T0, T2, T2 or T3 are true. 

The 1130 storage cycle consists of eight clock steps T0 through T7, with the first four used to destructively read out the sense bits of a core storage word and the last four used to write back the same or modified value into the word. 

This circuit feeds +Storage Write with the dot-OR output, so that we are in the write back portion of the cycle when we are NOT in T0, T1, T2 or T3. The output of the dot-OR gate also feeds through an SLT inverter to produce +Storage Read which is high whenever the dot-OR is low because it is T0, T1, T2 or T3. 

These output signals have a pullup resistor to make them sit up at +3V unless the transistor is conducting. Any of the dot-OR transistors conducting will thus result in 0V. If the dot-OR is high then the inverter gate transistor is conducting and +Storage Read is low; if any transistor in the dot-OR is low then the inverter gate transistor is turned off and +Storage Read is pulled high.

I put the scope on these signals with my board disconnected from the cables. All the wiring up to the cable connector was connected. The scope showed clean signals that went up and stayed flat at 3V for four clock steps, either T0-T3 or T4-T7. No noise, no glitch. 

GLITCH IS HAPPENING ON MY BOARD WHEN IT IS CONNECTED TO THE 1130

The noise shows up just as the first timer chip in a chain goes low, triggering the second timer chip in the chain to go high. The control signal (e.g. +Storage Read) then has the noise showing on its scope probe during that period of time, causing the control signal level to dip down below 2V which is seen by the first timer chip as a new trigger event. 

POSSIBILITIES FOR WHAT THE CAUSE MIGHT BE

Each of the sense output signals that will turn on the B register with the contents of a memory word are emitted during the high pulse of the second timer chip in the read chain. I believe this is about 8ma of current pulled for each output bit which is has a 1 value. Maximally I could be producing a word with all sixteen data bits at 1, which also requires the two parity bits to be 1, so 18 times 8ma or 144ma of current is being sunk over the cable from the IBM 1130 B registers. We have seen the retriggering is worse with higher number of 1 bits in the data word being returned.

This 80-100 nanosecond period of 144ma current flow might be inducing voltage on the control wires, although the sense bit signals are on cables T1 and T4 but the control signals are on the separate cable T3. More likely we have some kind of ground bounce between my PCB and the ground of the 1130 logic gates.

I have connected my board with a 16 gauge wire to the same ground terminal block that serves the logic compartments such as the one generating the control signals. If the 1130 itself is not suffering from detectable ground bounce, my board should be locked to it just as strongly. One layer of the PCB is ground, thus a very good path. However, we might still be getting some kind of bounce or resonance here that injects the noise into the control signals. 

I have a very beefy capacitor as a PCB buffer for the 3.3V power rail, plus wide traces for VCC, but the combined draw of the sense bits in that short time period might be pulling down VCC temporarily. I didn't see any signs of this nor of ground bounce when I used the scope on the VCC and ground pins of a timer chip. 

This may be some phenomenon of the particular timer chips when used in a chain - i.e. when the output of one ends as the trigger of the second. All the documentation for the chips covers them in single roles. 

Output of Schmidt Trigger after a bit more massaging

Here is the turn-on and turn-off points I am achieving against the 3V SLT signals such as +Storage Read. These are very satisfactory.

As you can see, it won't switch to logic high until the SLT line rises over 2.3V and it won't flip down to logic low until the SLT input drops below 0.63V. This is an appropriately large sledgehammer to stomp on the signal noise. 

The output that I have to down-convert in order to drive a CMOS input is swinging up to 3.0V when the signal is on and dropping to a bit over 2V when the signal is off. 

I will simulate a circuit that produces a sharp 0 and 3.3V output corresponding to the 2+ and 3V levels above. Still tweaking that part of the circuit. 

Investigations for 1130 MRAM board - ways to block retriggering of the timer chip

DESIGNING WIDE SCHMIDT TRIGGER CIRCUIT

I see that the noise that shows up on the +Storage Read or +Storage Write line dips from 3V down to just under 2V, which is enough to overcome the Schmidt Triggers in the timer chip. It thus looks like a request to trigger anew. A Schmidt Trigger is a gate with asymmetric on and off voltage levels. It has an upper and a lower threshold voltage, where it switches on only when the input rises above the upper threshold. It won't switch off until the input drops below the lower threshold. 

The thresholds on chips are set for modern signaling levels, such as TTL or LVCMOS 3.3V.  SLT has its own signal levels which are not the same as the modern devices. While I can get away with using LVCMOS 3.3 devices with SLT in most cases, SLT defines logic low at .3V or less and a logic high at 1.8V or higher with full high at 3V. 

The signal causing the problems shoots up to 3V and stays there, but has some noise that dips down to just under 2V briefly. According to SLT, that is a valid high signal and it never went to low. The timer chip devices a logic high as 2V or higher and a logic low as .8V or lower. The dip in the noise is seen as a brief change to logic low and a return to logic high - viewed from the timer chip - but is not an issue for the 1130's SLT logic. 

Texas Instruments datasheet for the SN74LVC1G123 chip states that the inputs have 'sufficient hysteresis to handle slow input transition rates with jitter-free triggering of the outputs.' The intent here is that a very slow signal change may wobble around the turn-on threshold voltage and be seen as many on and off transitions. Their design aims to reduce that risk by having different upper and lower threshold voltages. 

They don't define the threshold voltages specifically but the datasheet recommends minimum logic high inputs of 2V and maximum logic low inputs of 0.8V to work reliably with a 3.3V VCC. The noise on the input dips below the 2V for a very brief time, but sufficient for the timer chip to retrigger because it thinks it went low. The voltage thresholds are not handling this situation. 

I began to whip up a wider range Schmidt Trigger for the inputs, one I would set to turn on when a signal hits 2.4V and to not turn off until it drops to 0.8V. That is a sufficient span to ignore the noise on the input lines. I did this with discrete transistors and the aid of LTSpice to simulate the circuit at full speed (about 277KHz) for the input memory signals. 

Complications abound. The SLT output that drives the +Storage Read and +Storage Write signal uses a germanium transistor with a 750 ohm pullup resistor to +3V. The transistor has only a 0.3V drop due to the properties of Germanium, which is why SLT uses 0.3 as a logic low threshold. Worse, the 750 ohm pullup must be factored into any circuit receiving the signal as the voltage detected on the transistor receiving the signal will be divided down by a resistor in the trigger circuit. 

Thus if I have a trigger circuit with a 100 ohm common emitter resistor, the input voltage seen at the base of the transistor is 100/850th of 3V, or only about .353V which is below the 0.6V diode junction of modern silicon based transistors. I have to bump up the common emitter resistor quite a bit to get a good voltage swing for the incoming signal. This drops the current through the transistors making them a bit slower to switch. 

I worked up a circuit with a common emitter resistor of 1.5K that switches on at 1.85V and switches off a 0.9V. This is not the ideal range I envisioned but enough to work properly with the noise I am experiencing on the input line. The circuit produces an output that swings between 2.4V and 3V which I then have to convert to voltages that will trigger the CMOS input circuitry inside the timer chip. 

I don't have the detailed circuit of the timer chip, but I can model a typical CMOS inverter input and simulate until my design works reliably with the conditions I am experiencing. I am working on that final piece right now. 

I have been doing quite a bit of simulation, experimenting with the characteristics of the flat ribbon cables used in the IBM 1130 to deliver the signal to my PCB. Using the characteristic inductance, capacitance and resistance, I modeled SLT driver and receiver gates and looked for any kind of reflections or noise on the line in different conditions. 

I then modeled with an SLT output gate, the cable, and a CMOS inverter input gate to see if there was bouncing, ringing or other phenomena that might explain my situation. To no avail so far. Ringing or bouncing should happen on the rise or the fall of a signal, not 1 microsecond into a 1.6 uS steady signal. This is asynchronous to what is going on in the IBM 1130 so I have a very hard time believing that it is the cause of this glitching. 

If I have to build the Schmidt Triggers for the two inputs, it will add about thirty small parts to the design and require another expensive round of PCB manufacture. I think I could breadboard the trigger circuit and insert it temporarily just to see if I can bypass the problems. This does feel like a Rube Goldberg fix to a problem. I will be much happier if I can figure out why this is happening and can fix it at the source. 

Continued testing of 1130 MRAM board - results of probed points and added power wires

TRACES OF KEY SIGNALS AFTER CHANGES TO BOARD

No change with added power lines to the chips. A dead end I believe.

FOUND SHORTED OUTPUT LEAD ON WRITE TIMER CHIP

The reason my write timer chain wasn't producing pulses was a consequence of my having tacked a wire onto the lead to observe it. Somehow the trace came a bit loose and the trace plus lead moved over to touch the adjacent pin, which on this chip is ground. 

I removed the chip with my hot air station then soldered it back down with solder paste and the heat gun. The write time now fires when +Storage Write has a rising edge.

RETRIGGERING HAPPENING ON BOTH READ AND WRITE TIMER CHAINS

The same issue arises on the write timer chain - as the first timer output pulse ends, thus triggering the second timer, there is noise on the +Storage Write trigger signal and the first timer repeats. The write timers are on the other side of the PCB from the read timers, yet have the same behavior. 

WATCHING SOURCE GATE IN 1130 ALONG WITH RETRIGGERING AT PCB

The source signal from the originating gate in the 1130, compartment B A1 card J2, has the same glitching as the +Storage Write signal onboard my PCB. These are the same as what happens on the +Storage Read signal and its timer chain. 

Purple is source gate, yellow is input to my timer chip

This did get me thinking. Every problem like this is an analog circuitry problem, masked by the digital abstraction of timer chips or NAND gates. The timer chip does not come with a schematic of the internal circuitry thus I can't model this exactly. What might be happening inside the timer chip, the cable and the 1130 gate that could do this?

SUSPICION OF BACKFEED OF VOLTAGE FROM TIMER CHIP THROUGH ITS INPUT

I am wondering if the SN74LVC1G123 timer chip is somehow backfeeding the +Storage Write (and +Storage Read) lines as it finishes its timed pulse. The SLT logic in the IBM 1130 uses +3V for logic high and that is what we see on the +Storage Write line when it is active. The chips on my board, however, are operating at 3.3V not 3V.

What if the shutoff of the pulse somehow delivers 3.3V back to the input pin, perhaps through a protective diode, which then rings based on the impedance of the cabling and the details of the source gate in the 1130? When my board is disconnected, the signal from the 1130 looks great. When my board is connected, there is ringing even back at the source. 

EXAMINING DETAILS OF SOURCE AND DESTINATION GATES IN 1130

I will look at the analog circuitry in the gate producing the +Storage Write (or +Storage Read) signal and at the gate in the IBM core memory compartment that normally would have received the signal. That will give me component values that I can plug into models in LTSpice where I can see if I can explain the ring or resonance based on capacitance, inductance and the resistances in those gates and the cabling between them. 

Sadly I don't have the schematic for the TI timer chip to model its input properly, but I can make some assumptions and see whether I can explain the waveforms I am seeing. 

Continued testing of 1130 MRAM board - more probes added to zoom in on problem area causing retriggering

ADDED EXTRA ENERGY PATHS TO VCC AND GROUND ON THE NAND CHIP

I added wires to the VCC and ground pins of the 74HC00 chip to lessen resistance to current flow that might be causing voltage drops that 'bounce' the ground or 3.3V power flows to the chip. I previously did this for the SN74LVC1G123 timer chips that are retriggering, but the worst behavior I am seeing is coming from the NAND gate that drives the timer. 

RETRIGGERING EXISTED BEFORE MY TRIGGERING MODIFICATIONS

Originally the design had the +Storage Read signal directly connected to the timer chip trigger (~CLR pin) but I realized that this was a design defect, so I began to AND this signal with the +Storage Use signal before triggering the timer chip. The problem was that +Storage Read will always occur even when the storage cycle should not use memory, instead gating data from peripheral devices for example. 

The timer will ALWAYS produce pulses to set the B register bits for any bit of the MRAM chip on my board that has a 1 value. The MRAM chip will always output the value in memory of the word addressed by the current SAR register address bits, thus if any are a 1 then they will flip on the B register during cycles when it shouldn't, like the peripheral I/O case I mentioned. 

The modification I made to solve the incorrect B register setting issue mentioned above was to use one of the four NAND gates on the 74HC00 chip, reroute signals like +Storage Use and +Storage Read, switch the timer chip to trigger on a falling edge by changing the ~A, B and ~CLR input values, and connecting the newly used gate to the different trigger pin of the timer. 

Due to existing traces to the pads of the 74HC00 and timer chip, I had to cut traces, lift up some chip leads off the pad of the board, and use bodge wires. This is messy and caused several rounds of resoldering of the chips that might have introduced solder joint issues. 

I see the worst of the signal anomaly on the output of the newly used NAND gate, but I was having the retriggering problems before all this so the root cause predates the modification. My modification may be more susceptible but isn't sufficient to explain it. 

SOLDER JOINTS HAVE BEEN A PROBLEM WITH THIS BOARD

Putting the very small surface mount parts on the board is a challenge, since a soldering iron tip is larger that the space between chip leads. It is very easy to have blobs form across multiple leads causing shorts, which I had to wick up with solder braid. The resulting cleaned off joint might appear to be a good connection but not actually have metal fused between the bottom of the lead and the pad on the board. 

In hindsight I should have used solder paste and a hot air gun to solder the tiniest chips to the board, achieving a good connection without the messiness and errors that crop up with traditional soldering.