Very sporadic parity errors - need to capture evidence to find and fix

TYPEWRITER DIAGNOSTIC RANDOM PARITY ERROR WITH BIT 10 FALSELY DETECTED

I snapped a picture of a parity error stop that popped up randomly while the typewriter diagnostic was running. The 1130 was fetching the next instruction to execute from location x0258, which you can see from the Storage Address Register (SAR) in row 2. The process of fetching the instruction causes the Instruction Address Register (IAR) in row 1 to be bumped up by 1, which is why it shows x0259. 

The data read from memory is in the third row, the Storage Buffer Register (SBR), with xC220 showing. Looking at the listing for the diagnostic monitor running the typewriter diagnostic, at location x0258 is a LD 2,0 instruction - load from the address in index register 2 plus a displacement of 0. This would be xC200 but we have bit 10 turned on incorrectly. 

Each half of the memory word has its own parity bit which is set so that the total number of 1 bits in the half of a word plus that parity bit must be an odd number (odd parity). The left half has bits 0, 1 and 6 turned on, an odd number, so parity bit P1 is off (middle section of the display panel). The right side shows bit 10 on (the error) which would be an odd number of 1 bits put the parity bit P2 is set - triggering the parity stop. 

When the data in that location was originally being written as xC200 the right halfword had no bits set thus it needed parity bit P2 set to achieve an odd total. Somehow the data read back had bit 10 also set to 1. This could happen in the write or during the read. Alternatively, something else can inject a 1 bit at the time that the read is occurring in spite of the data from memory bit 10 coming back as 0.  

When originally written, the parity bit P2 is set but some error in the core memory might stick in a 1 in bit 10, because bit 10 is not inhibited to store a 0 value.  Core memory cycles always have a read phase followed by a write phase. Any bit that has a 1 value will cause a sense pulse during the read.

DETAILS OF THE MEMORY AND SBR CIRCUITRY

During read, all cores in the word are flipped to zero and any that had previously been set to 1 cause a pulse to come out of the sense amplifiers and into the SBR register. During write, any bit that should remain a 0 has a current passed through the inhibit wire, otherwise it will be flipped to 1 during the write phase. 

Failures in the inhibit or sensing function of core memory might cause the random false 1 bit to appear. 

Parity checking and setting are done with the SBR register. The SBR is the source of data for the inhibit wires during a write phase. It is the destination for sense pulses during a read phase. 

In addition, the structure of the SBR register circuitry has a number of pulses that could set bit 10 to a 1 value. These include transfers from the IAR register, from input output devices during XIO instructions, from the Accumulator (ACC) register during address computations, and the sense pulses coming for a read phase in core memory. A possible failure would be no sense pulse but one of the other pulses incorrectly arriving to set the SBR bit 10 to 1. 

SETTING UP A LOGIC ANALYZER TO CAPTURE AND FREEZE AT A PARITY STOP

I chose to use my DS Logic USB based logic analyzer to try to capture the cause of bit 10 being incorrectly set to 1. I only have 16 channels on the device so I can't record all relevant information - contents of the full 16 bit SBR, the 13 bits of the SAR that address the 8K of memory, as well as the pulses going into the SBR to set any of the 16 bits. 

I therefore will hope that these sporadic errors are always a falsely hot bit 10 and set up the signals to determine when/how that is occurring. I will monitor the parity stop flipflop and trigger the analyzer to stop when it is set. The trigger will be placed at the end of the buffer so that I can watch the signals that led up to the error. 

The IBM 1130 uses many asynchronous pulses, not aligned with the clock edges, which includes the sense pulses and the various pulses that set the SBR. I thus can't use a traditional logic analyzer mode that records the state only at a common clock edge. Fortunately the DS Logic analyzer can record such unclocked signals. It can also deal with the 0 and +3V signal levels of an 1130 system.