Plotter partially working, virtual 1403 printer progress

SAC INTERFACE FOR ADDING PERIPHERALS TO THE 1130

Debugging the resilient high speed link between fpga boards

The only errors I am seeing on the link are when I power the 1130 itself up and down - I suspect that the current temporary and thin gauge wire between the SAC box, slave fpga and other boxes needs to be made more robust. The numbers never climb very high - a handful of errors - and the resulting degradation of data flow is negligible.

Implementing physical plotter (1627 equivalent)

My diagnostics showed me that I had some signals inverted in my logic - the hardware interface to the plotter works with inverted command signals, so that the idle state is 1 and we drop the signal to 0 to command an action. I could see my deliberately slowed transaction started with all six commands at 0, flipped only the desired one up to 1 and then dropped it after a second.

Polarity is correct, the plotter clanked when I issued the command, and the interrupt and DSW actions were correct afterwords. Next pass, I will try to move the carriage left or right and the pen up or down. It is hard to see a carriage or drum movement because the pitch is so small, but I can clearly see the pen move up and down.

The up and down signals for the pen are reversed, so that a pen up command drops it onto the paper and vice versa. A quick change to the slave fpga logic and that was corrected. I need to build more extensive hand code to loop and drive the plotter a fair distance.

Implementing virtual 1403 printer

I did my first test of printing a line and bumped into a bug in the Python code, which I fixed up quickly. Second test after lunch tried this again and now discovered that I am reflecting the XIO Sense DSW up to the python program, when I should not. I did see that my XIO Init Write, to print a line, completed, issued an interrupt and provided the proper DSW bits (Xfer Complete and Print Complete) on the sense, then reset properly.

The Sense command should not be stored in the 'last XIO function' field and thus never seen by the Python code. That flaw is in the main fpga logic, which I corrected and synthesized, ready for the next test shot.

My goal was to print three lines, spacing between the first and skipping to channel 8 after the second. Wrapping up with a final space, I would then examine the output, The XIO IW gave the proper interrupt, but nothing was written to the output file. The XIO Control did not trigger the interrupt or add a space. I need to set up some diagnostics to get to the bottom of this. Overall, I am making steady progress debugging the virtual 1403 (and physical 1627) functionality.