Monday, June 13, 2016

Alto II CRT test tool designed


I am leaving in a couple of days for three weeks away, but will accomplish what I can while away for tasks that involve VHDL or Python. It has already been consuming quite a bit of time given a portion of the trip is my daughter's wedding.


The Alto has a monochrome CRT, in page orientation such that the vertical size is larger than the width. The documentation describes the signals that are sent to the CRT, which are very much like VGA or simplified NTSC video. We want to test and restore the CRT before we bring up the ALTO processor itself.

To support the testing, I will be creating an FPGA based tool to drive the video. I will be leveraging the patterngen open source code from open cores, building the tool for the low cost Elbert V2 development board. This board has a Xilinx FPGA and, among other IO options, a VGA connector. We will create a cable to hook the VGA port of this board to the CRT connector of the Alto.

I did the development work and some testing on my surface pro tablet, aiming to produce a binary file that the other team members can load onto the board when they want to do testing. I couldn't use my laptop because that had Vivado, which does not support the older Spartan 3 type chips, so I had to use the ISE toolchain on the surface pro.

There was some ambiguity in the video spec when comparing the known rate and display area size of the Alto manual to the timing ranges of the monitor manual. Since the display is interlaced scan at 60 fields per second, I need to complete 404 vertical lines in each field in order to support the 808 x 606 pixel display area. The specs for the monitor show it capable of 230 to 351 lines in a field, or 460 to 702 vertical pixels, not 808.

The team looked into the design question and studied other references in order to set a definite spec for the tool to produce. Once we have firm specs, it won't take long to finish up the tool and deliver it. Right now I am in waiting mode.

For those who know analog video, e.g. NTSC or similar, this is TTL instead. Three signals - vertical sync, horizontal sync, and video. There are no front or back porches, no negative sync pulses. The horizontal sync line just goes high for 11 microseconds once every 63 microseconds. The video signal is kept at 0 level to "blank" during the retrace time. Once every 60th of a second, the vertical sync line is set to 0 for 900 us then stays at 1 for the full time that all the horizontal lines are drawn.

Thus, once I have the specs for timing, such as 11us hor sync, 63 us line time and so forth, it is a simple matter of counters to drive the sync signals and to 'blank' video. Beyond that, any video pattern to be displayed has to be counted both in pixels across each line and in the line number to display. The Alto itself does this by fetching words for each line.

My design will algorithmically create vertical and horizontal bars, for example, but I can also precompute more sophisticated images and keep them in RAM for access during the scan.

We had discovered during our first day of restoration that the machine came with a Diablo 31 drive but did not have the disk controller card needed to access it. We are fortunate to know a collector who has spare controller boards and offered to give one to us for the restoration.

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