Sunday, August 28, 2016

Steady work on building up board


I set up logic to display various bits of information on the four 7-segment displays on the fpga board. It will be in hexadecimal. Each byte I select will be displayed on the two rightmost positions, which leaves me with two open displays. I will put the head number on display 1 and the actual sector number as it is detected by the drive on the second display.

When I ran a check to test out my code, the Adept utility thought it had written and read the data from the RAM, but it always came back all zeroes. Lastly, regardless of what I tried to write to any register, I always got zero back.

I checked for shorts before powering up my level shifting driver role extension board, connected to the FPGA board. I have everything laid out but want to work while I am fresh tomorrow morning, as there is potential to blow chips or even the fpga board if I make mistakes here.

While I worked on those problems, I also collected VHDL code to build a VGA display, ascii text only, which I would use to display the results of the latest sector read or written by the tool. I will be integrating this into the module slowly over the coming days, with the goal of having a quick display of the current sector and key other information that can be read off a monitor.

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