SPI link testing, designed interface PCB and sent to fab

INTERFACE PCB DESIGNED AND OFF TO FAB

The various parts of the Virtual 2315 Cartridge Facility operate at different voltage levels. IBM's SLT logic in the 1130 and its disk drive have a high of 3V. The FPGA operates on 3.3V signals and the Arduino Mega 2560 is a 5V device. Thus there are level shifters needed for signals moving between these devices. 

In addition, there needs to be a secure way of disconnecting and reconnecting the system to the IBM 1130 since ultimately the signals from the drive are accessed by wirewrap onto the backplane pins. I developed a board that will mount on the back of the disk drive, inside the covers of the 1130, which has two 40 pin IDE connectors on it. It is 5 3/8" wide by 2 3/4" high.

PCB

One IDE cable will be run to an IDC connector bolted to the side of the disk drive SLT card cage, with wires running to the points on the backplane where we access or drive the signals needed for the facility. The other cable will run to a connector on the box that contains the FPGA board, the Arduino board, an LCD screen, Pushbuttons, and the SD card socket. 

The only other part of the facility is a DPDT switch installed on the back of the drive that reroutes two signals from the drive. One is the signal from the electronics to load the heads, the other is a line that senses the state of the microswitch closed when the heads are down. This flips the drive between its normal (physical) mode and the virtual cartridge mode.

I have all the MOSFET transistors and resistors on order. The boards should arrive from the fab in about a week when I can solder it all up and test it out. 

SPI LINK TESTING

I used the scope to verify a number of the key link characteristics are correct:

• Clock period is 250ns for a 4MHz SPI link speed
• The clock is normally high when idle
• The bits are sampled on the rising edge of the clock
• Slave select bounds the exchange of an 8 bit byte on the link
• The bits are coming out on the SPI link in the order I expected

I set up a better testbench with more solid wire connections and good grounds between the FPGA, the Arduino and the scope. The FPGA is set up to show me the value received from the SPI link. All was ready to conduct the testing. 

I never got an error latch on the FPGA, thus it always passed the muster of having the second word be an exact inverse of the first word. Whether these are seen in the correct or the reverse order (bit 0 to 15 instead of bit 15 to 0) is not yet clear. 

The scope showed me the transaction ending with the good flag x5A5A but that will happen as long as we don't have the mismatch of the first two words. Again this suggests some degree of health in the link.

However, the two commands did not take effect. They should have toggled the FPGA between Ram to the drive and RAM to the SPI link, flipping one of the tricolor LEDs between green and blue. It stayed in whatever state I forced it to with the pushbuttons. 

Beginning of a transaction

End of transaction

For tomorrow I will be emitting some diagnostic data to help me debug the SPI code inside the FPGA. In parallel with that, I have begun to swap in a more powerful and well designed slave module I have used successfully in past projects. It requires a bit of redesign of the SPI handling logic but I believe this is worth substituting for the existing logic.