Resolved one anomaly and digging into the other, in the Alto disk tool

ALTO DISK TOOL

My first test today was to measure the clock frequency directly. It runs at roughly 45.5 MHz which gives a clock duration of about 22.2 ns. This accounts for the timing discrepancy. Time to figure out a more accurate timing method.

One possible complication is that different FPGA boards might run at other frequencies, so that a correction made to fit the board I am testing here might not work properly on a different board at Marc's house or one used by Al Kossow.

My solution is to use the external oscillator socket on the boards, plugging in some new 50MHz oscillator modules I am buying from Digikey. These are accurate to 30 ppm, which locks the frequency to within 1.5K of the target. I have no idea why my board is off so much but the tool must operate very close to the target in order to drive the disk properly.

I then set up the logic analyzer, which is a tedious effort, in order to watch the checksum calculation to determine what is throwing my written checksum off. The initial setup had some problem seeing a reliable clock pulse, so I reconfigured the fpga to output the clock on a different type of output pin, requiring a 40 minute turnaround of the toolchain.

I watch the checksum flip from its correct value to a wrong one - not sure where things are in the overall flow but emitting helpful signals will be the focus on the next round of changes. It appears that the seed is set properly as 0x0151 but the next word ORed in is 0x8342 which doesn't exist in the sector image.

My first record should stay with the checksum 0x0151 since the two data words are both 0x0000 and that doesn't alter the checksum. The second record would be seeded with 0x0151 and then OR in the eighth word of the label, 0x0079 which would produce a new checksum of 0x0128

Until I can know where we are in the process - which record and what 'word time' - I didn't have enough of a clue to spot the flaw. 40 to 60 minutes later, I was ready to test again. The checksum goes awry right away with the header record, first data word being handled.

The proper data is being written to the disk, but somehow the checksum isn't updated with that data. I will map out the FSM that writes the record to the disk, looking carefully at how the checksum is handled.

Good progress on the disk tool debugging

ALTO DISK TOOL

I set up a simulation testbench to closely examine the serializer, a module which loads parallel 16 bit Alto data words and shifts them out one bit at a time upon request from other logic in the disk tool. Symptomatically, I am seeing nothing but '0' bits shift out of the serializer and it never raises the signal asking for the next 16 bit word to be set up for loading. 

Most of my logic wasn't being executed. I stared for a while then saw it. My first test in the process checks to see if we are at startup, when an input signal is '1', to set up initial conditions. Once that goes to '0' it checks for the request to send the next bit and does its thing.

However, I coded the first test this way:

if loadword <= '1' then

The sequence <= means assignment, not a test for equality! The line actually forced the reset input signal to be on and always passed that first test. It never got to my other logic to serialize and emit output.  It should have read if loadword = '1' then

With that moronic error fixed, the serializer began to work. I could move back from simulation to the real testbed and see that I was now emitting the signals that I should. I could zoom back out and watch the actual written stream to verify that it wrote the preamble, sync word, two header data words, checksum, postamble, etc.

I found the system emitting the preamble of zeroes, the sync word and first two data words, but the checksum being emitted was incorrect. Further, once it wrote the postamble the clock shut down and the remaining two records were not attempted.

It is time to hook up the logic analyzer and record what occurs during the writing of the first field. I will also capture the running checksum since the first problem I saw was an incorrect checksum being written. 

The watchdog logic shut down the write sector operation before the first record was complete - clearly wrong behavior. I temporarily turned off the watchdog logic and was able to write the entire sector on the testbed.

The overall pattern and data content appears good, at least up to the first data word of the label (second) record in the sector. I looked at the signal which is output by the serializer each time it is ready for the next word to be loaded and the count between the sync bit of the two records was indeed 14 word times, just what it should be.

The sync words are correct, the two header record data words are correct, the postamble of that record and the preamble of the label record is correct, the sync word for the second record and its first data word match exactly.

However, two things are not perfect yet. First, and most seriously, the checksum being written out is not correct. Second, the length of time between words is a bit too long, so that the fourteen word times I wrote out take over 158 us to produce when the expected duration is closer to 135. An 18% elongation of each bit cell would produce this timing.

I will be simulating the bit cell timing machinery tomorrow to either fix it or determine that I have a problem in the oscillator on the FPGA board. If the fpga board runs a bit slow, at 4.24MHz instead of 5 MHz, it would create this behavior.

More work on IBM 1130 display panel upgrade

IBM 1130 DISPLAY PANEL UPGRADE

I began disassembling the existing IBM boards and wiring inside the display panel pedestal box. The boards and attached lamp holders were pulled from the white plastic honeycomb and all the yellow signal wire clips were detached from the rear of the boards.

Lamp holder and PCBs pulled out of honeycomb prior to removing yellow signal wires

Signal wires laced in position, by row, for attachment to my boards

The signal wires are laced together by the IBM manufacturing plant with each of the six rows grouped together and the wires for each column position exiting along the bundle at the appropriate point. This makes it easy to attach all 96 register signals to the right pins on the boards.

A terminal strip on the right side (from the rear) brings up the AC, lamp test and common voltages and distributes those to the individual PCBs for each row. I detached the lugs from the PCBs and removed the mass for storage, just in case someone wants to restore this to original condition in the future. 

Removed innards to be replaced by my upgrade

My three PCBs will sit flat against the honeycomb blocks, having the signal pins on the side facing the rear of the machine for attachment to the yellow signal wires. The PCBs have three turret connectors to wire them to the AC, lamp test and ground lines at the terminal strip. On the front side of the PCB, facing the honeycomb, are 2 pin header sockets where each light should be placed. 

Honeycomb blocks with a paper image of one board placed roughly where it will sit

There will be a huge increase in room inside the pedestal box with my boards in place. They are pulled back to gain access to the 2 pin socketswhere each light is plugged in, in the event that a bulb burns out and needs replacement. 

I will remove each light bulb from the existing plastic holders. These bulbs have wire leads that I will wrap around a 2 pin male header, slide a short section of paper straw over the exposed pins, and plug into a socket on the PCBs. First up, I have to remove all the working bulbs from their IBM holders in preparation for installing them in my new holders. 

I haven't fabricated the holders that will keep the boards in place against the honeycomb, with the bulbs sticking forward into the honeycomb at each location that should light up. I expect to use some rubber insulation as a standoff between my PCB and the honeycomb, thus I will wait to measure the size of the holder until the PCB is in its final location. 

Wire lead bulbs in the IBM oval plastic holders, attached to the IBM PCBs

I made up a sample light assembly to see whether I need to make any adjustments to my plan. If the bulbs are susceptible to too much tilt or misalignment, it will make it very difficult to get all 96 to slide into their holes simultaneously when I install the big board. 

The bulbs themselves are quite small, leaving plenty of margin to fit into the hole, although the 2 pin header on the bulb is oriented vertically while the honeycomb holes are wider horizontally than vertically. I had no choice, a horizontal layout for the sockets didn't leave enough room for the thyristors and other parts. 

I was able to solder in a miniature bulb onto a pin socket, rather than a machine pin header, with excellent control of the orientation and stiffness. When I attempted this with an original bulb used in the 1130, a much larger cylindrical bulb, I found the leads too oxidized to solder readily. Fifty years of oxidation built up quite a thermal barrier. 

Mini bulbs soldered into pin socket - bottom socket a quick and dirty test

Testing bulb and socket with thyristor circuit

Even if that were solved with plenty of flux, the bulbs are close enough in diameter to the hole in the honeycomb that alignment becomes too critical. With 96 bulbs in the matrix, even a few off center by a small amount would block the PCB from fitting into place. The solution is to exclusively use miniature bulbs, considerably smaller than the holes. 

Original IBM bulb with oxidized leads

IBM bulb holder, wedges into hole in honeycomb block

ALTO DISK TOOL

I set up an extension board on the fpga, allowing me to tie various inputs to 0 or 1 level and to loop back some outputs to the inputs. The goal is to drive a sector write operation without having a real disk drive attached, so that I can debug everything at home. Waiting for a few hours at Marc's lab is dragging this out way too long.

With the testbed set up, I began observing status signals emitted on the PMOD connectors where I had output likely signals that would point at the malfunctioning section of logic. With only a few minutes work, I focused in on the logic that is misbehaving.

This appears to be another of those cases where VHDL logic that appears correct does not work in the real world. The serializer should be counting bits as it shifts them out, raising a signal to request the next word when the last bit has shifted out. The raised signal isn't raised. Tomorrow I will set up a test driver and synthesize the behavior of the module.

Finished designing PCBs for the 1130 display panel, ordered all remaining parts, boards to foundry

IBM 1130 PANEL UPGRADE

In addition to the two swapped thyristor and output socket components, I found that some of the 2 pin headers, which align the lamps to the holes in the 1130 panel, were misplaced slightly. I realigned all the sockets and properly placed the register 2 bits 4 and 5 components. 

Next< looked over the detailed signal and power routing, finding many suboptimal layouts that I could improve by manually routing traces. In many cases, signals were routed on the bottom side of the board and vias placed to move the signal between top and bottom, when there was a direct top side routing possible. 

Right side is autorouted with extraneous use of vias, left side is hand routed alternative

I was able to remove most of the vias (through holes that conduct a signal from one layer to another). I also bumped up the trace width of the power lines (from the anode of the thyristor (big pad) to the 2 pin header that connects to the lamps.  Now satisfied with how the board is configured, I printed an actual size copy on paper and verified alignment inside the 1130 pedestal panel. 

Vertical clearance will be tight, requiring the board to be tilted to get inside the pedestal box, but will fit in place with enough room to work properly I think. I will measure the height inside the box precisely as a cross check. I did compensate by every so slightly shrinking the height of the board, taking a smidgen off the top and bottom margins and even a bit off the left edge. 

Final layout for the PCB that drives the 16 x 6 register display

I also test fitted the actual thyristor and resistor parts on the paper copy to be sure that I didn't make a stupid error. Those appear fine as well, giving me adequate clearance between physical parts. The thyristor, resistor, turret connectors and 1 pin headers all fit on the top surface of the board, while the 2 pin headers are placed on the bottom side with only their pins sticking up for soldering on the top layer. The only soldering required on the bottom layer is for the 1 pin headers. 

Since this is so tight, the order in which I solder everything will matter. I am not sure whether the resistor or the thyristor goes first, but the headers get soldered last. The turret connectors are fasted with nuts, not soldered, depending on mechanical pressure to make a good electrical connection. 

With this presumably ready to ship off to the PCB manufacturer, I started in on the two boards that handle the remaining lamps inside the pedestal, each an 8 x 6 matrix of possible lamp positions. In practice, the 1130 does not use all 48 positions on either board, but I could lay this out symmetrically and omit components on the unused positions.

I copied and cut down the schematic and PCB files, before making the remaining adjustments necessary. There is not a wide free area for the three turret connectors, thus I will have to be clever about where I place them to have a usable board that can fit in the spots required.

In fact, I noticed that part of the bottom row of lamps is unused on both boards, so I simply removed row 6 columns 4, 5, 6 and 7. That gave me plenty of room to move the three turret connectors and still have a small board that will fit side by side where it has to inside the 1130 pedestal box.

Small PCBs to implement the remaining lamps (other than the six major registers)

The pedestal box has a matrix of 5 x 5 plastic honeycomb units organized as two rows of seven blocks each. Horizontally, each hole may be used but vertically, only the odd numbered rows have lamps installed. Thus, the six rows of the panel sit on rows 1, 3 and 5 of the top honeycomb block then on 1, 3 and 5 of the bottom block.

Honeycomb blocks (1 is missing in the picture)

There are a total of 35 lamp positions horizontally across all the blocks, but only 30 are active. The registers sit in the rightmost 16 spots (viewed from the rear of the machine), thus take 3 whole honeycomb blocks plus on position of the next block. One open position sits to the left of the last register lamp, which is open space to accommodate the edges of my big and little PCB boards.

One of the small boards implements six lamp holes, the leftmost honeycomb plus one hole in the adjacent one. My board covers eight holes horizontally, however, so my board sits across two more hole positions in that adjacent block.

The block has two remaining hole positions, that will remain free or have just a smidgem of the small board edges over them. The other small board sits over the next eight hole positions, en entire block plus two holes of the block shared with the end of the big board.

Counting from left to right, in the rear, for the 35 possible lamp columns implemented by the seven honeycomb blocks, we have my first small board covering holes 1-8, the second small board covering holes 11 to 18, and the large board covering holes 20 to 35. The edges of the left two boards have holes 9 and 10 open and will have no problem fitting side by side.

The edges of the middle (small) and right (big) PCBs have just row 19 open to accommodate them, but that is sufficient for them to fit side by side. There is 1" between the centers of the end lamps of the adjacent boards, but they have less than 1/2" of margin from the lamp on their edges.

I will remove the mini PCBs that are the original IBM mounting spots for thyristors and to which the bulb holders are fit, detaching the wires from the terminal blocks which feed them. This will be saved so that the machine could be restored to original condition if someone so desired.

The turret connectors arrived today, spurring me to purchase all the 2 pin sockets and header strips needed to finish the construction of the boards. I picked up paper straws, which I will use as a barrel to hold the miniature light bulbs soldered onto their 2 pin headers so they can be plugged into the sockets on the boards.

Next up, I shipped off the boards to the foundry, using PcbUnlimited.com to panelize them. I should get them in about two weeks. Nice high quality 4 layer boards that cost almost $250 including shipping.

I am excited enough about this that I will go out and begin removing the original holders right now. I do have to separate out all the bulb holders, because once I have the headers and straws I can remove the bulbs and begin assembling all the plug-in lights.

Alto event planning, work on IBM 1130 panel upgrade and on disk tool

ALTO DISK TOOL

I attended a meeting today at Computer History Museum to discuss holding an event to celebrate the Xerox Alto and other innovations, leveraging a few restored machines and many of the people who made those inventions. We also had staff from the museum, both historians and the live event producers, plus Marc, Ken, Luca and me for our restoration team.

Some of the people at the meeting who worked on these systems at PARC and are going to help with the upcoming event: Chuck Geschke (co-founder of Adobe), Doug Fairbairn (a founder of VLSI Technology), John Shoch (former president of Xerox Office Products Division and venture capitalist).

A number of the current staff of PARC were there too and will be involved. We expect to have the Alto we restored, at least two Altos restored by Al Kossow, a networked link to an Alto at Living Computer Museum, and hopefully Bruce Damer's machine which we are attempting to restore.

I did some diagnostic work during the brief time we had at Marc's lab today. I found that my synchronization between the various state machines involved in writing was not working properly, leading to a sector with nothing but zero output bits

I attempted to read a cartridge that wasn't archived properly earlier, but all records of all sectors had checksum errors reported. I used a scope to capture sector 0 on read of the cartridge in question. The data appears properly formatted so the issue is some regression error when I updated my logic.

IBM 1130 PEDESTAL LIGHT UPGRADE

I thought I had everything placed properly, it routed successfully and I worked my way through the minor manufacturing issues, such as silkscreen component outlines touching via hole pads. I was almost done when I spotted two light positions whose components were swapped around - register 2 (Storage Access Register) bits 4 and 5.

PCB layout - some swapped components to be corrected

While I could swap the input signal wires, it ruined the symmetry of the trace lines and complicated that section. I therefore planned to move things into their intended place and manually draw the traces to connect it properly. As you can see from the picture, it is a very dense board where the parts barely fit in place. 

Building PCB design for IBM 1130 light enhancement, plus working on disk tool debugging

ALTO DISK TOOL

I think I have worked out some light modifications to allow me to trigger my disk tool for writing, without having an actual disk drive attached, such that I can capture the stream being written to debug any further bugs.

I was ready to make the changes, but had to find where I stored my FPGA boards in order to load the logic onto it. I spent a bit of time putting in the changes to help with testing tomorrow. We should have a good session tomorrow at Marc's home, collecting data to get my cartridge writing logic working properly.

IBM 1130 UPGRADED PEDESTAL LIGHT DISPLAY

I launched the PCB design software and began to tediously build the panel that supports the 16 lights each for the six registers (IAR, SAR, SDR, AFR, ACC and EXT). This board will have 96 thyristors, 96 resistors, 96 single pins for the signal inputs, 96 double pin headers for the lamp attachments, and 3 turret terminals to provide power, ground and lamp test voltages, capable of delivering 1A on AC and ground turrets when all lamps are lit.

The design begins with a schematic to define all the connections, which I built up first by drawing a single register of 16 circuits and then replicating that six times across the sheet. When I transfer this to the PCB for layout, I will have hundreds of parts to find and place in the correct location.

If I left the sequentially assigned part numbers, such as JP3 for an input pin or D34 for a thyratron, the layout would be extremely tedious and error prone. I took the time (considerable mind numbing time) to rename all the parts with a logical structure that instantly identifies which light position they implement. Thus, S103 is the input signal for register 1, bit 3. T311 is the thyristor for register 3, bit 11. R200 is the resistor for register 2, bit 0. and O415 is the 2 pin header for the lamp for register 4, bit 15.

With this, I can find and drag the parts to their desired locale on the PCB. The only parts with strict locations are the output (2 pin) headers for the lamp mounting. The power headers and the various signal pin headers just need approximate siting - signals near their thyristors and the power turret terminal in the right edge zone.

This first PCB, for the six registers, will be 8 1/2" wide and 4 1/4" high. The right hand 1/2" is the zone for the six double-pin power connections. The lamps are separated 1/2" center to center running left to right within a register, and the register rows are separated 3/4" center to center from top to bottom. The board has a 1/4" margin on three sides and 3/4" on the power connector edge.

The remaining lights in the pedestal will be covered by two identical but smaller boards, each hosting an array of six rows of eight lamps each. Some lamp positions are not implemented, depending upon the signals being displayed and the arrangement of the faceplate.

Faceplate - registers on left half, status at mid right and other data on right

One board handles the mid-right section that has the T and X clock states and various status lamps, while the other board on the far right covers the op code, registers, interrupt levels, and so forth. One design will produce both of the smaller boards, with the board sparsely populated to fit its role.

The schematic relabeling of the register board took many hours to complete, before I could lay out the physical board and place components. I wasn't done with the relabeling until the evening. Therefore, I am just beginning on the layout.

However, I found that spacing will be much tighter than I expected, because the spacing between lights is just 1/2" horizontally and 3/4" vertically. The SCR is more than 1/4" by 7/16" which fills a lot of the space between adjacent lights in the grid. The resistors and signal pins are easy to fit, but the SCR is the dominant factor.

I tried out a different organization to see if I can get the parts to fit in the tight grid. I rotated the 2 pin header from horizontal to vertical orientation. This allowed the thyristors to fit between the columns of lights and my 0805 sized resistor and signal pin will fit as well. I had to lay out an entire row across the top and the entire left column to ensure that everything fits.

The only unknown is routing. The path from the resistor and input pin is very direct to the thyristor, as is the path from thyristor anode to output pin. Further, the ground and AC voltage lines are on the inner planes of the four layer board, saving the need to route those lines. The only line that will be significant for routing is the lamp test signal.

It will take me another day to finish laying out all the components across the board before I can attempt the routing. 

Adjustments made to disk tool

Maker Faire took place these last few days and I was busy volunteering as an examiner for amateur radio license testing, for attendees who wished to get or upgrade their ham radio licenses. Since the FCC requires a ham license to transmit video from a drone, in addition to the usual reasons people become hams, we were fairly busy. I worked the first shift every day. 

ALTO DISK TOOL

While at the ham testing booth at Maker Faire waiting for the show to open to the public each morning, I did some work on the disk tool to clear up the synchronization issues when writing images to disk cartridges. Of course, this requires testing to validate but this looks promising.

I also tweaked the reading logic to be independent of recorded clock pulses from the disk drive once the checksum of each record is read and tested. The Alto switches from the disk drive clock line to its internal clock at this point, just as it uses the internal clock to count off the preamble time before it looks for the sync word beginning each record.