IBM documentation is almost always correct, but it can frequently be less than helpful too. The SLT Packaging manual contains these two images on the same page. The first is the numbering of pins on the ceramic inside the SLT can. The second is a completed can showing the printing on the cover and the location of pin 1.
The upper diagram does not contain any indication of the side from which it is viewed - bottom or top of the can. It seemed logical that it was the underside view and that numbering would start with pin 1 on the left bottom as shown in the bottom photo and then proceed to the right across the bottom.
It does not. The numbering is viewed from inside the can or above it, but not rotated the same way as the photo below. The correct numbering begins with 1 at the bottom left and proceeds up the left side, across the top, down the right side and then fills in the center with the voltage rails if needed. I spent a few confused minutes trying to make sense out of pin numbers for signals compared to the circuits in the can.
TRACING THE TWO SINGLE SHOT OUTPUTS
I was able to trace the two output signals from the card pins D02 and B02 up to the proper pin on the SS SLT can. This was mildly complicated by the existence of a resister between the SLT module and the card pin, but at only 10 ohms it was easy to locate. The two single shots are both implemented in the one SS can at the bottom right of the SLT card when viewed from the front.
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| Bottom right can implements the two SS gates |
Pin B02 is signal -Phase A SP A and pin D02 produces signal -T Clock Adv SP. Later I will trace out the other components for these gates, such as the resistor packs, inductor and FDD diodes involved, lastly reaching the inputs to the SS gates and their location on or off the card.
IDENTIFYING THE FOUR FLIPFLOPS BY TRACING OUTPUTS FROM THEM
Next I looked at the outputs from FF gates that run to card pins and beeped out the connections to discover which physical FF can represents each of the four FF gates on the board. This was very straightforward since the card pin and SLT can pad are directly connected.
Referring to the picture above, we have rows counting from top to bottom and columns counting from left to right, identifying the 24 SLT cans in a way that I can use to identify where gates are implemented.
We get signal -Start Advance at pin B04 coming from the Qnot output of the FF gate just to the left of the single shots at the bottom. This can is therefore the Advance flipflop from the ALD. In the second row from the top, right hand column, we have an FF that produces the signal +OSC TGR at D13 from its Q output and signal -OSC TGR at J12 from its Qnot output. This is the OSC flipflop.
Signal -Run Prog Ld Not SRP or PT Resp at pin B07 from the Qnot output of the flipflop that is the fourth row down and second column from the left of the card. This is the RUN flipflop from the ALD. Lastly, the flipflop in the bottom row, second column from the left produces signal -Delay on pin D05 from its Qnot output and is therefore the Delay flipflop from the ALD.
NEXT UP, THE OTHER LOGIC GATES ON THE CARD
The remaining logic gates are functions like AND and OR, strung together to control the state of the flipflops and the pulses from the single shots. They also pass along the reset signal throughout the machine and the clock phases A and B. Those foundational signals run to many different destinations, thus they need strong drivers to handle the big fan-outs. I expect to find the HPD (High Power Driver) modules associated with those outputs.
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