More on the new DE10-Nano board approach

POSITIVE CONSEQUENCES

My old design had to implement the memory interface to drive the DDR3 RAM, FIFOs to handle various clock domain crossings, and multiple clocks to drive the memory interface. All of these depended on intellectual property (IP) from Xilinx and these were the areas that were misbehaving in the old design.

The new approach has a single clock domain on the FPGA side and its AXI interface for communications between the FPGA and the Arm hard processor side implicitly handles clock domain crossing. Thus, no need for FIFOs. No need for defining clock PLLs or dealing with the inability to route all clock signals over the high speed clock networks of the Digilent board; the choices they made for connecting RAM and clocks did not support enough clock buffers to get all the required clocks on the same side of the FPGA chip in the dedicated clock lines. 

The DDR3 RAM on the new board is handled by the hard processor (ARM) side entirely, so I am not involved at all in memory interface controllers or the details of RAM access. Simple memory mapped transactions across the AXI bridge will let me read and write to RAM with simplicity. 

While I still have transactions between the Linux hard processor side and the FPGA side, there are no external wires carrying signals nor need to do voltage level shifting between FPGA and Arduino. Thus the inherent reliability is higher. 

NEGATIVE CONSEQUENCES

I have built an interface level converter board that converted some few signals to +5V for connection to the Arduino which managed the SD card for disk cartridge images and the user interface LCD. Now that everything is handled on a single board which uses LVCMOS 3.3V signaling exclusively, I have to reroute those signals to the new voltage levels. 

I have some sunk cost in the Digilent board, the Arduino Mega 2560, the SD card daughter board and the LCD interface daughter board as well as VHDL logic I built for this configuration and C code for the Arduino. Some of the logic I built is unnecessary as it was used to exchange transactions between the old boards, but I will need to rewrite parts of my FPGA logic and create a new interface program for the Linux processor side. 

Since I was challenged getting the old approach to work reliably, this is no longer an issue. My biggest costs (other than the new board and LCD interface) is in the learning curve to switch over to Quartus toolchain and master the new type of board. 

Terasic has a touch screen LCD daughter module which I ordered and will use for the user interface. While the board has an HDMI port, that is way too powerful for what is needed and would involve quite a bit of coding just for good video. Using this touch screen module should ensure a fast development path.