Time to shift to entirely new board and toolchain for the virtual 2315 project

RECENTLY AWARE I HAVE ATTENTION DEFICIT HYPERACTIVITY DISORDER

Those who look back over my blogs and notice the huge number of projects that I got partway through and then wandered on to new things will have spotted this major symptom of ADHD. After 71 years of ignorance, I discovered and was diagnosed with ADHD. 

Now painfully aware of the risks of wandering on to another more novel project or challenge, I was determined to finish the virtual 2315 cartridge project and then wrap up the renovation of the IBM 1130, ignoring the temptations of shiny new endeavors. Other than the holiday and family times, I have been working to get the system working, failing with great frustration. 

TIME TO DITCH VIVADO AND XILINX FPGA BOARD, TAKING A NEW DIRECTION

I have had many days fighting erratic behavior of the Vivado toolchain. As an example, when programming the FPGA I will now receive dozens of "Background task busy" pop up errors. Reboots and every other change has no effect on this. 

Yes, this might be errors on my Lenovo laptop, on the Windows operating system, or corruption on the Xilinx Vivado installation, but nonetheless it is almost completely blocking any forward progress testing and debugging my design.

Opening the integrated logic analyzer cores might produce error messages about mismatch of port numbers, yet the files that actually drive Vivado are hidden beneath a byzantine and flaky user interface. With no documentation to highlight which files are actually controlling behavior and where they sit, it is extremely difficult to figure out and correct such cycles of failure. I suppose this is obscure in order to protect intellectual property, but it makes the tool pretty useless to me right now.

I can run the synthesis, suspecting that the memory interface is not working thus bringing out the signal that shows initial calibration is complete; this proves that the memory interface did not come ready. I make minute changes just to show via LEDs that each of my three clocks are indeed clocking, when the calibration magically works properly. 

In several months, I have had virtually zero of my logic at issue, but spent inordinate time with odd behavior inside memory interfaces, clock modules and other IP I don't control. The fact that sometimes I see correct operation shows me that I am writing and reading from memory, and receiving SPI transactions coming from the Arduino, but I have failed to get a solid transaction sequence that loads a sector and then retrieves it successfully.

I refactored the logic many times, including overly conservative interlocked approaches and very formal state machine construction. I pored over the list of errors and warning messages. I set up integrated logic analyzers to try to spot where things are going awry.

I kept finding sporadic errors before everything degraded to where I can't get logic analyzer cores working at all. It is time to toss in the towel since I am not moving forward on the project and don't see the likelihood that something will break the logjam any time soon. 

NEW PLATFORM CHOSEN

The existing design split the work into two sides - an Arduino that would manage an SD card for the cartridge images and the user interface, talking over SPI to the FPGA board that would interface with the disk drive. The capacity of a 2315 cartridge requires 16 megabits of storage, beyond the block RAM capacity of the FPGA chip. The board I had chosen had plenty of DDR3 RAM to hold the image. 

The new platform for development is a Terasic DE-nano, which uses an Altera/Intel system on a chip. It gives me a hard processor with twin ARM cores running Linux plus an FPGA. The FPGA can easily access the capacious DDR3 RAM from the hard processor side. The board provides an SD card socket accessing from the Linux side and an HDMI output for an improved user interface. 

This makes use of an entirely different toolchain in addition to giving me an integrated single board platform for the entire project. Of course I will have the learning curve of adopting the new tool and FPGA chip, but I am expecting that I will be free of the capricious and frustrating issues of the last few months. Sadly, my past experiences with Vivado and Xilinx based boards had all been good - the IBM 1130 interface expander and the Xerox Alto disk image extraction tools, for example.