CORRECTED TEMPORARY WIRING FOR V2315CF
I had failed to connect the sense line for power failure from the main Virtual 2315 Cartridge Facility (V2315CF) box to ground. This is a pullup input pin on the PICO processor that will be pulled to ground by a circuit on the Power Distribution Board as long as the +12V from the IBM 1130 power supply is active.
My logic requires this to be low for normal operation, such as loading a virtual cartridge image. When it goes high, if a cartridge is loaded the V2315CF drops File Ready and immediately unloads the cartridge image back to the microSD card in the Mini 2315 Cartridge.
I had also built the new version of the 2310 Interface Board, one that contains a relay and MOSFET to drive the Unlock lamp on the IBM 1130 console when in virtual mode. However, I discovered that the real/virtual switch was not being detected.
After a brief investigation, the cause was apparent. One of the contacts from the switch was not actually soldered to the trace underneath it, although it looked like it was. I repaired that quickly and got the V2315CF to load the virtual disk cartridge successfully. The drive did its 90 second warmup and then the drive was ready for access.
STARTED 309 DIAGNOSTIC AND IMMEDIATELY STOPPED WITH A PARITY CHECK
After a bit of poking around, I realized that regardless of what data we stored into core memory locations 0 to 4095, bit 13 would be set to 1 whenever the location was next read. This was the same symptoms I saw a few weeks ago, which seemed to go away by reseating a card. Obviously it is a borderline condition that comes and goes. Time to find the root cause and fix it - once again diverting me from the final checkout of the V2315CF through successful execution of the disk function diagnostic.
WATCHED A FEW SIGNALS TO CONFIRM THAT IT IS A FAILURE TO INHIBIT BIT 13
I can see the bit detected by the sense amplifier - it is detected whether we write a 0 or a 1 into the word. I also see the circuit trying to inhibit the write so that the bit stays at 0, when we want the value to be that. This is a current through the inhibit wire that opposes some of the X and Y write current trying to flip the core. By opposing enough current, it keeps the core from reaching the level where it will flip magnetic state.
The most telling clue was the oscilloscope image of what the inhibit waveform looks like when we successfully inhibit bit 12, compared to the image of the waveform for bit 13. I built a differential connection as specified by IBM, using a twisted wire pair terminated by 150 ohms to ground at the scope inputs.
The inductance seen by the voltage on the two wires produces the sloping wave, as energy is absorbed. There is also a reverse EMF when the magnetic field collapses as the voltage source is cut off. The non-working bit, on the other hand, shows a pure voltage on the two wire ends with no slope. This tells me that we have little or no current flowing in the inhibit wire.
Inhibit wires have three connections because there is a center tap with each of the other wires running through 2K cores of the 4K total served by these connections. When the inhibit driver is working during a write (when we want the bit to stay 0), there is current flowing through each 2K wire to the center tapped ground.
The resistance across the two ends - one for each set of 2K cores - was a low single digit value. However, the resistance between each end and the center tap was about 128 ohms. It should be a low single digit value. With this relatively high resistance the amount of current flowing through the inhibit wire is too low, allowing the X and Y driver current to flip that core to a 1 value. We see no reverse EMF in the trace for bit 13
Interestingly, even without the center tap having a good low resistance connection to ground, the sense amplifier can detect the pulse during a read, when we flip all the cores to the 0 orientation. The induced pulse is reliable. Thus, our center tap issue is mainly affecting the write cycle where the wires are used for inhibit, with little impact when they are used for sense.
SIMILAR ISSUES TO OTHER FAILURES IN THIS CORE MEMORY MODULE
We have had several failures in the core memory module on this computer. Most of them involved the connections to the sense/inhibit wires. In all the cases, the broken connection was on the PCB on the bottom of the core stack which routes signals from connector blocks to the edge where discrete wires carry the signal to the core planes.
I went through several gyrations to bridge the signal from the core planes, where the sense/inhibit wiring was always intact going through the cores themselves, getting it connected to the circuitry in the compartment that surrounds the core stack. Had any breaks been inside a plane, where teeny wires are threaded through thousands of small cores, it would have been much more difficult to repair.
CONSIDERING WHETHER I CAN REPAIR THE PCB OF THE CORE STACK
With all the welded and soldered connections to many small wires on each of the 18 core planes, all the wires running between the planes and down to the bottom PCB, and many wires running up and down on the outside of the planes, it seemed impossible to open up a stack so that I could separate the planes and PCBs.
However, I do have a core memory stack of very similar technology. I believe this one was used with an IBM 1800, a sister computer to the 1130. The main difference is that the 1800 has some additional memory addresses (AUX area) that can be used; the 1130 does not use these areas. It is banged up and definitely not usage. It was marked to be scrapped. It does, however, let me try to open the stack up as much as I can since there is no risk of damaging a working 1130.
The last picture above is of the bottom PCB that is used to interface the core stack to an SLT board that has support electronics ringing the stack. The connector blocks you see fit through tiny drilled holes in the SLT board and stick up alongside pins that are installed on the SLT board. A jumper block is plugged over the mix of SLT board and core stack pins, connecting the signals together.
The connector blocks carry the X and Y addressing signals as well as the sense/inhibit signals. The bottom PCB is actually a sandwich of two PCBs, not a multilayer board but two separate PCBs sandwiched together. Around the edges of this PCB sandwich, pads are connected using "S" clips that clamp the boards together.
The PCB that is visible has traces for the X and Y addressing lines. Diagrams in the Automated Logic Diagrams (ALDs) for the core storage show these patterns, which are the ways that signals from the edge connect to common wires that run on the other side of the bottom PCB (bottom of the two PCBs in the sandwich).
However, we do not see the traces for the sense/inhibit wires. These are connected near the corners, also using S clips, but the traces are on the upper of the two PCBs in the sandwich. The pictures below show the traces running from the sense/inhibit S clips which will connect to pins on the connector blocks in the central area of the bottom PCB.
The sense/inhibit wires are twisted pairs of white and blue, plus a black common wire. They are soldered to the small S clips on the edges and tack welded to the ends of the wires at the core plane. I do have access to the wires and to the ends that come out of the core planes.
PLAN OF ACTION FOR REPAIRING THE INHIBIT BIT 13 DEFECT
Based on what I see from the partially disassembled scrap stack, I will look for a good low resistance ground connection from another bits wiring, then bridge that to the black wire for bit 13. It is slightly less desirable that the individual ground connections with controlled traces (I assume) on the upper PCB of the bottom PCB sandwich, but should work well enough.
HACKED THE POWER DISTRIBUTION BOARD TO CONTINUE TESTING
The power logic for the V2315CF involves a battery, a charger/maintainer, the 12V from the IBM 1130, a time delay relay, and the power supply for the main V2315CF box. The Power Distribution Board was central to this functionality, including a circuit that detects when the 1130's 12V supply stops so the V2315CF can do an emergency unload of the virtual cartridge if it was loaded. The timer disconnects the battery after 40 seconds of battery only operation, sufficient for the unload.
A flaw that I missed resulted in KiCAD grounding the connection from the time delay relay to the power supply. This caused a big pop when I first triggered the relay to test the 40+ second battery power for the power supply. It blasted a trace apart inside the time delay relay.
I repaired the relay, then got to work on the Power Distribution Board. Since I had a ground plane across the bottom of this PCB, KiCAD made the connection to ground by connecting the terminal screw 10 pin to the ground plane with four thermal relief pads. It also connected the hole where a diode was inserted to feed the power supply, putting in four thermal relief connections to the ground plane.
I grabbed my trusty knives and dug away the copper thermal relief connections, disconnecting screw terminal 10 and the diode hole from ground. Once I verified that it was isolated, I returned to my testing of the power logic.
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| Yellow circles where I removed the thermal relief connections |
This time, when I triggered the time delay relay with 12V that would be coming from the IBM 1130 12V source, it connected the power supply to the central bus. Since the battery was feeding the bus, the power supply turned on. About 40 seconds later, the relay dropped the connection and the power supply was off.
I do have replacement boards coming that do not have the incorrect grounding, avoiding the need to rework the boards with an Xacto knife. When they arrive I will switch the parts over to the correct board. I have one more test to perform, once I connect the battery charger/maintainer to the board. I will have the charger hooked to 115VAC, everything else in place, with a bench power supply standing in for the 1130 power supply.
The test will be to first run with the bench power supply, seeing the V2315CF power supply turn on and stay that way. Next I will switch off the bench supply. The V2315CF power supply should remain on for about 40 seconds, using the battery, then switch off. While this is happening, I will watch the signal output that is the power fail warning to the V2315CF.
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