Repair of IBM 1130 core memory with failure of bit 13 inhibit in lower 4K

ROLE OF INHIBIT WIRES

Core memory consists of a memory plane for each bit in a word. X and Y address lines select one core in a 2D grid on that plane. A third wire passes through each core, which IBM sometimes refers to as a Z wire. It is a wire that passes through all the cores on that plane, however, whereas a one X and one Y wire only cross in a single core.

Core memory is read by sending current in one direction (we will call this the Read direction) in one X and one Y wire. That current will try to flip the magnetic field of the core to an orientation we will call 0. The same Z wire that is used for inhibit is also used to sense the value of the core; if the core being addressed as previously magnetized in the 1 orientation, the flip of the magnetic field will produce a pulse in the sense/inhibit wire. Thus, we find out what is in a word by setting its bits to 0. This is called destructive read. 

To write into core memory, we reverse the current direction (now we call this the Write direction) in one X and one Y wire. Where they cross, the core involved will be flipped to the 1 orientation. If we don't want to set the bit to 1, but instead want it to be zero, then we have to inhibit the flip of the core. 

Magnetic cores have a threshold current that must be reached for its orientation to flip (to either 0 or 1 orientation). The current in an X or a Y line is less than the threshold. Thus, all the cores along the X or Y wire are not flipped except for the one that receives current from BOTH X and Y. 

If we send a current in the Read direction through the sense/inhibit wire, the net current in the core is now below the threshold and it doesn't flip. A Read direction current in the sense/inhibit line while we have a Write direction current in X and Y results in the core being set to (actually remaining) the 0 orientation. No inhibit, the core is set to 1 orientation. 

For engineering reasons, the core stack in an IBM 1130 is divided into four sections of 2K bits each. The upper and lower 4K have their own circuitry. Within a 4K section, however, the current loss due to resistance in the sense/inhibit wire during inhibit would be too great if it passed through all 4096 cores. Therefore, one wire runs through 2048 cores and a second wire runs through the other 2048 cores. One end of each of the two wires are connected together (called the common). 

During a read, the sense/inhibit wire ends are connected to a differential detector. When a core flips during a read, the pulse is detected across the two ends, even if the common connection to ground was not high quality.

The use of three wires for sense/inhibit is important to understand because the common point is wired to ground, so that the inhibit current flows through the two wires to ground. The driver for inhibit switches on a transistor to conduct current through a wire to the ground (common), while a mirror driver conducts to send current through the other wire to ground. 

Sense both ends see +6V conducting through the drive transistors, if there is no ground then there will be no current flow. It is only with a good ground at the common point that a current flows through the sense/inhibit wires and can block the flipping of the core. 

The connection point for the sense/inhibit wire triplet is on the top or bottom of the core stack, as shown in this diagram. We are concerned about inhibit for bit 13 in the lower 4K of the core stack. The connections are circled in green. The three wires from bit plane 14 come out on the A side (top of the stack when installed in the machine). These are on the right as viewed from the front of the core stack. 

Along the edges of the PCB at the base of the core stack, the portion closest to the SLT board upon which the stack is mounted, there are small S clips where the sense/inhibit wires are soldered. Counting from the right edge, looking down on the top of the core stack, clips 16, 17 and 18 carry the bit 13 signals from the two senses wires and the common wire, respectively. The wire triplets are white, blue and black - black for the common point. 

THE FLAW WE ARE FIXING

The common connection for bit 13 has much too high a resistance. The fault, as with all the others, is in the PCB sandwich at the base of the core stack, where it routes the signals to connector blocks that project pins through the SLT board for connection to the electronics. This lack of a low resistance path to ground causes the sense/inhibit wires to have essentially no current during a write cycle, allowing the bit to always flip to a 1 state. 

THE FIX

Since the common wire is ultimately connected to ground in the electronics, I can just cut the black wire from the edge S clip, add additional wire length to it, and bring it up to solder onto a ground pin on the SLT board. This will restore the path for current to flow when we inhibit a bit during a write. 

However, the wire broke off the common terminals at the edge of the core plane. I had to solder a new wire onto it, which I then routed to a ground point. The memory is starting to accrete many bodge connections to compensate for failing traces inside the core stack - although not within core planes. 

TESTING CORE SHOWS THE ISSUE IS RESOLVED

I wrote all zeroes across memory and read them back successfully. I also wrote all ones and that was correctly retrieved. This whacks the latest mole, so that until the next one pops up, I can get back to the disk drive functionality diagnostic testing.  I did run some code for a while, with one random parity check popping up. This leads me to suspect that there are more flaky connections in the stack.