INTERFACE BETWEEN 1130 AND CORE MEMORY
The interface is asynchronous, which eliminates the need to tie to the 1130 clock in any way. Based on the address being accessed, the appropriate core memory module is presented with +Storage Select. The 1130 logic asserts +Storage Use when it wants to do a storage cycle which is always a read followed by a write.
The CPU raises +Storage Read during the first four 1130 clock cycles of each set of eight. The CPU raises +Storage Write during the second four 1130 clock cycles of the set. Since a clock cycle is 450 nanoseconds or 275 nanoseconds, depending on the speed of the core installed, this is either a 3.6 microsecond or 2.2 microsecond storage cycle. +Storage Read and +Storage Write are only approximately arranged relative to the 1130 clock.
Core memory has destructive read, thus a storage cycle must write back the value that was in the word after it has been read. The core module addresses the particular word of memory during a cycle, sending current through the X and Y axis wires to flip the core towards the magnetic direction that represents a zero bit value.
If the core had previously been magnetized in the opposite direction, which represents a one bit value, then the flip of the magnetic field induces a pulse in the sense/inhibit wire that runs through all the cores in a plane. It is the asynchronous arrival of this pulse that sets the Storage Buffer Register (SBR or B) to a 1 value. No pulse arriving leaves the B register set to a 0 value.
The B register now has the value that was destructively read out of the word. The cores are all magnetized in the zero bit value direction. The write cycle that immediately follows will write the value from B back into the cores.
The write cycle sends current in the opposite direction down the X and Y wires, causing the core to flip to the magnetic direction thar represents a one bit value. Any bit in the B register that had a 0 value must have its core blocked from being magnetized during the write. This is done by sending a current through the sense/inhibit wire against the flow in the X and Y wires, thus inhibiting the core from flipping. No inhibit current means the core will flip to the one bit value direction.
As long as the +Storage Select and +Storage Use signals are asserted, whatever address is presented on the address lines from the Storage Address Register (SAR) will select an X and Y wire to pick an individual word of memory. +Storage Read and +Storage Write alternate as long as the CPU is not stopped, driving first the read and then the write.
When the +Storage Read signal goes high, the core memory sends the current through X and Y to reset the core to the zero bit value direction and any cores that were not already in that direction will produce a pulse on the sense/inhibit line. That pulse sets the B register to the value that was read from the word in core.
When the +Storage Write signal goes high, the core memory sends current through the X and Y to set cores to the one bit value direction. Any B register bit that is zero causes the sense/inhibit line to block that particular core from flipping, thus remaining in the zero bit value direction.
Therefore my interface is the B register values as input, the sense pulse outputs, the SAR address as inputs, and the four control signals +Storage Select, +Storage Use, +Storage Read and +Storage Write.
In addition to the sixteen data bits in a word, the 1130 employs two additional parity bits. Thus there are eighteen sense output signals. The B register provides 16 bit values as input. Some circuitry in the CPU calculates the proper parity and sends the P1 and P2 values as input to the storage.
OVERVIEW OF MY CORE MEMORY SUBSTITION BOARD
The heart of this circuit is an Everspin MR0A16A Magnetoresistive Random Access Memory (MRAM). This chip has 64K words of 16 bits, is compatible with ordinary SRAM access patterns, and operates at 35ns. It can be read and written an infinite number of times without any degradation. It is non-volatile for at least 20 years when power is removed.
The chip has bidirectional data pins, which are controlled by the output enable pin ~G so that the chip is driving an output when we want to read but when deasserted the chip can be driven with new data values to write into memory. The ~W pin requests a write of the data on the data pins into the addressed location of storage. The ~E chip enable pin is what we assert to cause a read or write (with the ~G and ~W pins appropriately sets. This chip supports independent access to the two bytes of the word, but we will keep the ~LB and ~UB pins asserted at all times to work in full 16 bit word mode.
Because the 1130 has two unidirectional data buses - B register and sense output - I will use a tristate buffer chip so that I only assert the B register and parity bit values when the chip is in write mode. In read mode we will route the data bits from the chip to a simple circuit that produces a pulse for any 1 value data bits about 800 nanoseconds after the +Storage Read goes high. I will also assert the B register/parity bit values to the chip about 800 nanoseconds after +Storage Write goes high.
The circuit will have a voltage regulator to produce the 3.3V needed for the MRAM chip and related chips. The design of the MRAM chip will deactivate it when the power rail drops below 2.7V and won't activate the chip until the rail reaches at least 3.0V.
I will feed the regulator from the 1130 system's +12VDC power supply. This supply is connected via a relay when the 1130 verifies that the three primary logic rails are stable at the proper voltage levels. If any of the power supplies sags, the machine is switched off, or the building power fails, this relay opens which immediately drops the +12V supply. This means we can't write anything unless the CPU logic is fully operational with good power and we will block writes well before the CPU logic rails drop.
The 1130 puts its core memory in a separate card cage, either gate B compartment C1 or in gates D and E in the extension frame. It is connected to the rest of the system via three SLT connector cables that plug into the top of the card cage at positions T1, T3 and T4. I only need to provide SLT pins in the same arrangement as the backplane to allow those cables to be plugged into my circuit instead of the card cage.
Mechanically, I will place the circuit board above the card cage but below the top grill of the card cage, right where the three SLT cables attach. The only other connection needed is a pair of wires to the +12V and ground lines.
The MRAM chip needs to be shielded from stray magnetic fields that can disturb the stored values. I will put a metal faraday cage around the chip on the PCB to provide this protection. I believe that with surface mount parts, I can make a board that fits in this space, however if not I will work out an alternative.
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