REPAIRED DETACHED CONNECTOR FOR PIN G02
The connector that was pushed back off the PCB needed to be reattached. I removed the plastic covers, then soldered that connector back in place by hand. I used a clamp to hold the connector down at the front and applied the soldering pencil tip further back to melt the solder underneath and make it flow.
I noticed that the metal pad had been peeled back, validating the theory that the connector had been mechanically sheered backwards as it was inserted into a socket. I didn't like the shape of the connector, so I switched to another that was in better shape. The card fits into sockets and the connector seems to be holding in position.
BENCH TESTING
I have a test jig where I can plug in SLT cards (including my substitute card for this project) and get access to the signals on the various pins. By supplying this with +12V power and appropriate signal states, I should be able to test out the behavior of the card on the bench. The outputs are connected to oscilloscope probes in order to view the action of the board.
FIRST CHECKS DONE
I brought up power to verify the voltage regulator and lack of excess drain. I immediately discovered that I had to +5 and ground connections to the FPGA board reversed. I removed the pins and installed jumper wires to power the CMOD S7.
The command lines to the plotter are inverted logic and had the expected 12V level when they are not asserted. The detection circuit that tells my logic whether the plotter's -24V is active (when the plotter is cabled up and switched on) did give a logic high 3.3V when the -24 power supply was switched on and a logic low when it is off.
DRIVING THE BENCH TESTING
I grabbed an Arduino and programmed it using direct port access because that gave me more precise timing for the output control signals from the Arduino that drive my plotter card - 500 nanoseconds per port manipulation which is close enough to an 1130's T clock steps that I could mimic the timing well enough to test out my card. The Arduino will drive the inputs to my card.
// port D bits 0 to 7 below#define XIOW 0#define A5 1#define T6 2#define XIOS 3#define XIOS15 4#define DCRESET 5#define B0 6#define B1 7// port B bits 0 to 3 below#define B2 8#define B3 9#define B4 10#define B5 11// reuse analog inputs as digital inputs for control#define resetit 14#define doup 15#define doraise 16#define sense 17#define sensereset 18#define doboth 19void setup() {pinMode (XIOW, OUTPUT);pinMode (A5, OUTPUT);pinMode (T6, OUTPUT);pinMode (XIOS, OUTPUT);pinMode (XIOS15, OUTPUT);pinMode (DCRESET, OUTPUT);pinMode (B0, OUTPUT);pinMode (B1, OUTPUT);pinMode (B2, OUTPUT);pinMode (B3, OUTPUT);pinMode (B4, OUTPUT);pinMode (B5, OUTPUT);pinMode (resetit, INPUT);pinMode (doup, INPUT);pinMode (doraise, INPUT);pinMode (sense, INPUT);pinMode (sensereset, INPUT);pinMode (doboth, INPUT);// DCRESET is inverted, true when lowdigitalWrite(DCRESET, LOW);// below control inputs are standard, true when highdigitalWrite(XIOW, LOW);digitalWrite(A5, LOW);digitalWrite(T6, LOW);digitalWrite(XIOS, LOW);digitalWrite(XIOS15, LOW);// below control inputs are inverted, true when lowdigitalWrite(B0, HIGH);digitalWrite(B1, HIGH);digitalWrite(B2, HIGH);digitalWrite(B3, HIGH);digitalWrite(B4, HIGH);digitalWrite(B5, HIGH);delay(500);// release the reset from the boarddigitalWrite(DCRESET, HIGH);}void loop() {// process any button pushesif (digitalRead(resetit) == HIGH) {// hold reset for half a second then releasedigitalWrite(DCRESET, LOW);delay(500);digitalWrite(DCRESET, HIGH);} else if (digitalRead(sense) == HIGH) {// simulate the 1130 executing an XIO Sense Device for plotter// one memory cycle (8 T clock steps)PORTD |= (1 << 3); // XIOSPORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD &= ~(1 << 3); // ~XIOSPORTD &= ~(1 << 1); // ~A5} else if (digitalRead(sensereset) == HIGH) {// simulate an XIO Sense Device with reset bit 15 turned on// one memory cycle (8 T clock steps)PORTD |= (1 << 3); // XIOSPORTD |= (1 << 1); // A5PORTD |= (1 << 4); // XIOS15PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD &= ~(1 << 3); // ~XIOSPORTD &= ~(1 << 4); // ~XIOS15PORTD &= ~(1 << 1); // ~A5} else if (digitalRead(doup) == HIGH) {// simulate an XIO Write with B Bit 2 set (move pen up)// one memory cycle but only activates at T6 clock stepPORTD |= (1 << 0); // XIOWPORTD |= (1 << 1); // A5PORTB &= ~(1 << 0); // ~B2PORTB &= ~(1 << 0); // ~B2PORTB &= ~(1 << 0); // ~B2PORTB &= ~(1 << 0); // ~B2PORTD |= (1 << 2); // T6PORTD &= ~(1 << 2); // ~T6PORTD &= ~(1 << 0); // ~XIOSPORTD &= ~(1 << 1); // ~A5PORTB |= (1 << 0); // B2// wait 1 millisecond then execute XIO Sense Devicedelay(1);PORTD |= (1 << 3); // XIOSPORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD &= ~(1 << 3); // ~XIOSPORTD &= ~(1 << 1); // ~A5} else if (digitalRead(doraise) == HIGH) {// simulate an XIO Write with B Bit 5 set (raise pen off paper)// one memory cycle but only activates at T6 clock stepPORTD |= (1 << 0); // XIOWPORTD |= (1 << 1); // A5PORTB &= ~(1 << 3); // ~B5PORTB &= ~(1 << 3); // ~B5PORTB &= ~(1 << 3); // ~B5PORTB &= ~(1 << 3); // ~B5PORTD |= (1 << 2); // T6PORTD &= ~(1 << 2); // ~T6PORTD &= ~(1 << 0); // ~XIOSPORTD &= ~(1 << 1); // ~A5PORTB |= (1 << 3); // B5// wait 1 millisecond then execute XIO Sense Devicedelay(1);PORTD |= (1 << 3); // XIOSPORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD &= ~(1 << 3); // ~XIOSPORTD &= ~(1 << 1); // ~A5} else if (digitalRead(doboth) == HIGH) {// simulate an XIO Write with two B bits set// B Bit 5 (raise pen off paper) and B Bit 4 (move pen left)// one memory cycle but only activates at T6 clock stepPORTD |= (1 << 0); // XIOWPORTD |= (1 << 1); // A5PORTB &= ~(1 << 3); // ~B5PORTB &= ~(1 << 2); // ~B4PORTB &= ~(1 << 3); // ~B5PORTB &= ~(1 << 2); // ~B4PORTD |= (1 << 2); // T6PORTD &= ~(1 << 2); // ~T6PORTD &= ~(1 << 0); // ~XIOSPORTD &= ~(1 << 1); // ~A5PORTB |= (1 << 3); // B5PORTB |= (1 << 2); // B4// wait 1 millisecond then execute XIO Sense Devicedelay(1);PORTD |= (1 << 3); // XIOSPORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD |= (1 << 1); // A5PORTD &= ~(1 << 3); // ~XIOSPORTD &= ~(1 << 1); // ~A5} // do nothing if none of the buttons were pushed}
For example, asking the plotter to move the pen is done by issuing an XIO Write instruction to the plotter device (area code 5) and setting on bits 0 to 5 of the data word to request pen left, right, up, down, raise and lower commands. In the 1130, one 3.6 microsecond memory cycle is when the controller card sees the XIO Write by means of signals +XIOW and +A5 that are high for the entire memory cycle. During one T clock step of that cycle, signal +T6 is high. The data word is sitting in the machines B register thus my card sees signals -B Bit0 thru -B Bit 5.
To see the status of the plotter, a programmer issues an XIO Sense Device to the plotter and receives back a data word where bits are assigned specific status conditions by the controller card. The card sees +XIOS and +A5 for a memory cycle, at which time it turns on B bits 0, 14 or 15 based on the conditions of the plotter as determined by my controller card. My card has to pull down lines -DSW0, -DSW14 and/or -DSW15 based on the conditions it is reporting. The XIO Sense Device can take place while the plotter is still moving the pen, before any movement has been requested, or after the movement is complete.
If a particular bit in the command word for the XIO Sense Device is set (bit 15) then the controller card will turn off its request for the 1130 to be interrupted (on interrupt level 3). When a movement is completed, the controller card turns on the interrupt request and maintains that until an XIO Sense Device with reset bit 15 is executed.
My board has six inputs that I wire to pushbuttons or slide switches on my breadboard bench testing device:
- Put the controller card in reset, as if the 1130 has powered up or has RESET pushed
- Issue an XIO Write to move the pen up
- Issue an XIO Write to raise the pen
- Issue an XIO Sense Device
- Issue an XIO Sense Device with reset bit 15
- Issue an XIO Write to move the pen up and raise it
I installed two open collector hex buffer chips on the breadboard so that the +5V outputs of the Arduino become compatible with my cards logic levels (0 and 3) with a pullup resistor to +3V. These run to the pins of the controller card.
Four of the outputs of my card need a +3V pullup resistor, which I put on the breadboard. The other outputs of my card operate with logic levels of 0 and 12V. One special input of my card takes -24V which would be delivered by the 1627 plotter when it is powered on, through a 3.9K resistor which I put on the breadboard.
I set up the scope to monitor some of the outputs and inputs, so that I could verify that the controller card works according to spec. Once it is all verified, I can plug it into the 1130 and test with my physical Calcomp 565 plotter which is the same as the IBM 1627.
If the 1627 plotter is not hooked up (or powered down), then an XIO Sense Device should not pull down -DSW15. Any XIO Write request should immediately turn on the interrupt request and pull down -DSW0 for any XIO Sense Device. There should be essentially zero delay. I then hooked up the -24V to the board and moved on.
The function pushbutton doup will issue an XIO Write requesting an up pen movement. The -Up signal drops from its regular state +12V for 1.9 milliseconds. Within a millisecond, the card sees an XIO Sense Device and will drop signals -DSW14 and -DSW15 to zero for one memory cycle.
After 3.8 milliseconds, the -Interrupt Level 3 request will drop to zero and stay there. Pushing the sense button should cause signals -DSW0 and -DSW15 to drop to 0 for one memory cycle.
Pushing the sensereset button will return the same but turn off -Interrupt Level 3 and subsequent sense receive only -DSW15.
Pushing the doraise button is similar to what occurs with doup, however the signal -raise is held low for 50 ms and only after 100 ms will -Interrupt Level 3 drop to zero.
The button doboth will simultaneously request moving the pen left and raising the pen. The -left signal should go low for only 1.9 ms but the -raise signal should stay down for a full 50 milliseconds. Only at the end of 100 ms should the -Interrupt Level 3 drop low.
Pushing the resetit button will reset the card to its default state. That would turn off the -Interrupt Level 3 line and any commands to the 1627.
DISCOVERED A MAJOR FLAW IN THE PCB DUE TO A DEFECTIVE FOOTPRINT
Once I attempted some tests I discovered the reason that my +5V and ground connections were backwards. The footprint I used with KiCad has reversed the position of some of the banks of pins.
As you can see above, banks J3 and J4 do correctly position the +5V pin (24) and the ground pin (25) they way I had to rewire them. My footprint had J4 at the bottom right and J3 at the top right, thus reversing where the +5 and ground pins sat. It also meant that my PCB wired signals to J4 when I intended them to be wired to J3 based on the digital I/O pin numbers 16-23.
QUICK AND DIRTY REWIRING AND REGENERATION OF FPGA LOGIC
In order to proceed with testing, I altered the configuration file for the CMOD S7 to put my signals on pins 25-31 so that they were picking up what was routed to the top right connector, since the footprint swapped the pin numbers for the right side. Because pins 32 and 33 are analog inputs, I removed the pins from the CMOD board and then added jumper wires to carry the signals down to what the footprint thinks are pins 16 and 17.
I only had to reroute signals on the PCB from 32/33 to 16/17, as well has swapping +5V and ground, in order to have accessibility to all the signals. I then changed the configuration file for the FPGA to make use of the actual pins where the signals were connected, which made everything right for now.
I will have to redo the PCB with a repaired footprint in order to have future builds work properly, as well as regressing the configuration file changes, but I can make use of this board with bodge wires without needing to fab and put parts on a new version of the PCB.
CORRECTED INVERSION OF 1130 OUTPUTS
My testing showed that the outputs to the 1130 -IntLvl3, -DSW0, -DSW14 and -DSW15 were being emitted by my FPGA code as inverted logic but the open collector inverter chip on the PCB was flipping it back to high when asserted. I changed the FPGA code to emit high when asserted, thus the PCB will produce the inverted values needed.
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