Completed SAC Interface 1130 side IO capability, working on PC side

I completed more logic definition during the long flight from London to Los Angeles and on the ground switching flights, but didn't arrive home until the evening. As a consequence, I didn't do any construction or hands on work in the garage that day and today is Thanksgiving so I only got out for a few minutes today.

SAC INTERFACE FOR ADDING PERIPHERALS TO THE 1130

I completed the functionality to support up to 20 devices with the SAC interface, each configurable on the following dimensions:

• area code (device address)
• XIO functions supported
• Use of cycle steal
• Interrupt level(s) used
• Priority of devices for cycle stealing

I am building some black box modules that the synthesis tool will assume are producing real input signals and/or are consuming some of the signals I generate. If I didn't do this, the synthesizer would recognize when outputs weren't used, trimming away all the logic to create them, Similarly, if there is no input or it is a fixed value, logic is trimmed away or replaced by a constant output. 

Careful attention to the synthesis report and all its fussy warnings is a best practice for successful designs, as these warnings may show a flaw in the logic or a missing connection. Even when it is purely noise, a bit of modification to the source can remove most of them. In that way, any warnings that do arise as you make changes have a reasonable chance of flagging real issues. 

I did some work on the link to a PC, which provides data, control and status for an emulated peripheral, but still have some design decisions to make before it can be fully implemented. 

It will leverage the Digilent provided USB system using the async parallel port mode, a quick way to allow code on the PC to send or receive data from a pool of up to 256 one byte 'registers' which are whatever signals I need. These will be the data out and in buffers, plus status and control information, for each of the implemented peripherals.

The logic to transfer pairs of registers (16 bit entities to match the 1130 architecture) is in place in my VHDL, ready to be used for functions inside the interface. The first two I will implement are a cycle steal access to memory and a display/update of SAC interface signals.

To create the PC side code, I set up Visual Studio Community, the free version of VS. I will use Python for my code unless I find some technical impediment to using the Digilent Adept software with that language.

I received the FMC Carrier S6 FPGA board, the Xilinx breakout board that attaches to it, and the parts for the plugs to connect my signals to the breakout board. In addition, I picked up a set of HP standalone probes - a logic probe, a logic pulse injector, and a current probe - that will be handy to identify which of the many drivers of a wired bus is driving the output to 1.