Wednesday, November 19, 2014

More design and development work on the SAC interface box

I am flying over to London today (Wednesday), which burns up a couple of days but potentially gives me free time to code up VHDL - if not too foggy from jetlag. Looking forward to visiting a few museums in my off hours and a working 1130 up at the National Museum of Computing.

I received a great tip from a reader of the blog - suggesting I use a current sensing probe to deal with those wired-OR circuits where it is otherwise hard to sort out which incoming line is active. The probe can tell me which incoming line is consuming power driving the gate. Very neat, avoiding the necessity of tracing circuits backwards, pulling cards or lifting wire wrap.


All things considered, I decided to order the Xilinx XM105 debug card which breaks the FMC high pin count connector out to provide the 126 signals on header pins for easy connection to my SAC interface boards and other connectors for peripherals I will support. The breakout board will be at home along with the fpga board upon my return next week, allowing me to move directly to wiring everything together for my first tests with the 1131.

I determined the proper molex connectors and pins to mate with the square pinned headers on the Xilinx board and ordered them. I went through my design docs and assigned pins on the breakout board for the various SAC signals as well as annotating the role of each pin on my FPGA VHDL code.

A few design items remain - I want to use the 24VAC power signal voltage from the 1131 to power my interface box up and down. I will need a 24V relay to be consistent with the IBM approach, plus a compatible power connector to enable use of the power cable that hooked to the CHI box.

I also have to build the 3V regulator and install the power supplies. Physically, the fpga board needs mounting and I should use the PC power supply 12V line rather than the fpga board power brick assuming the unit can supply the required current and power quality.

While I am programming the initial functionality for the fpga I will code a communications protocol over the UART over USB cable, allowing a PC terminal program to send and receive data from the interface box.  I want this as generalized as possible yet not so tricky that it takes too long to build and debug. 

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