Tuesday, March 24, 2015

SAC Interface debugging work, finding bad solder points on interface cards


Upon investigation, what I discovered was that a power pin (SLT +3V) was loose in the connector to board three, which delivers 12 of the 16 bits from the B register, one of the most visible sets of signals and ones I used to make sense of the incoming stream. In addition, on board 1 which was hand soldered (out of impatience) before I finished my flow solder oven, four of the twelve receiver circuits had transistors which weren't properly soldered to the pads.

After a bit of resoldering on the four known transistor issues on board 1 and a reseating of the pin for board 3, I was ready to test again with the 1131 powered up. It did show me all the T clocks now, which had been masked by the bad transistor positions, but I see that one of the X clock signals coming from the 1131 isn't valid. I have to determine if this is a wiring problem in my connector, the cable or something bad back in the 1131 itself.

I am also triggering the 1131 to take interrupts on all four levels. Even when I reversed the logical sense of the signal I am emitting, the same problem happens. I am not sure what is causing this but will do more investigation. It could be residual junk from the FPGA logic that will control this lines in the future.

I turned my attention to the driver circuits on card 1, because it is on the top and easy to access. I found that, just as with some of the receiver circuits on that card, I had some bad solder points for the transistors on a few circuits. I did some resoldering of transistors and checking, at least until I ran out of daylight.

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