Wednesday, April 22, 2015

Now handling cycle steal fetch requests and status inquiries from PC to the SAC Interface Box

Today was slightly better than yesterday, so a bit of time became available at the end of the day and I got in to work on the system.


I used my instrumented logic to shake out several functions, so that I can now load the memory address that will be used for cycle steal fetch and store, as well as retrieving the contents of a chosen memory location. I do have a timing bug I had to chase, because I had to fetch twice from the same location in order to receive the value of that core address. If I changed addresses, I still got the contents of the location from the last fetch request.

Status messages are also being correctly processed, sending me the status value being maintained in the box. When I tested a store into a memory address using cycle stealing, I found I was addressing memory but storing zero rather than the data pattern I sent. I suspect this is related to the timing mismatch that causes my fetch to be one request out of sync - likely I am storing before picking up the intended memory contents.

Daylight was waning by this point, but I had some good insights based on the testing. Time to go through my logic, find and fix the 'last fetch not current fetch' issue and be sure my data value is what is passed to the store logic.

I have some more code cleanup for the Python program and more logic I want to add to the fpga, some of which I will do tonight.

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