Wednesday, April 1, 2015

Validated last of the lines for the SAC Interface box, ready to begin testing certain FSMs

I spent some time at the Computer History Museum today, rather than working on the 1130 system, plus the usual day job workload, but I did managed to make some progress on the SAC Interface.


I modified my fpga logic to emit zeroes for both channel data and channel address lines except when the XIO E1 signal  is on. This hopefully will help me do the verification of the incoming data lines, using XIO instructions.

When I fired up the system for a test, I was no longer cramming bits onto the B register line, which is good, but without raising the Channel Write Gate line at the proper time, my Channel Data In bits won't be seen. They certainly are not visible on the console. XIO E1 is dropped by the time a normal adapter would be putting up the sense word.

I used my VOM to do some continuity testing between the 1131 backplane for various key signals such as Channel Write Gate, Block Clock Advance, Meter In and Advance IO Entry, and the pin on the SAC interface cards. This let me definitively identify the correct line for each of those signals. I also cross checked XIO E1 while I was at it.

Now that I am sure of the signals on each line and the correctness of my circuits to drive and receive them, I am ready to try out my cycle steal FSM as well as a sample Sense DSW FSM. These are coded up in my adapter logic, but I will work on a shortcut to trigger the cycle steal read and cycle steal write FSMs from two of the temporary buttons I have attached. The Sense Device FSM will be set to trigger on any area code, so that it will respond to all XIO Sense Device commands.

Tonight I will work on the changes to trigger the FSMs as described above and some other test support functions, in preparation for testing of low level behaviors such as cycle steal read or write of a memory word and device sense presentation.

I will also put in some diagnostic output information on the USB link to the PC and display it in the Python program, to help me see what is happening inside such as the state of the FSMs and their outputs. 

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