SAC INTERFACE FOR ADDING PERIPHERALS TO THE 1130
Implementing virtual 1442 card reader/punch
I rolled in the logic to handle the interrupt request and reset, plus the logic to latch in each column for the XIO Read or update the punch buffer for each column after the XIO Write. The last bit to add was the logic to pretend that an XIO Init Read was issued, so that the Python program can extract the updated punch buffer at the end of a read/feed/punch cycle.
I did a quick bit of testing and discovered a need to refine the overall logic between the fpga and pc. The problem is in handling a feed cycle, which should copy the pre-read buffer to the pre-punch buffer and signal an operation complete. Another problem was is in triggering an operation complete when a stacker select is processed.
Not totally completed with the rework, at least in the time available today to work on the system.
At least I have started into testing and hammering this device function into operation. It needs a jumper to prevent the 1442 inboard electronics in the 1130 from recognizing XIO instructions, allowing the FPGA to handle them instead.