Implementing and testing virtual 1442 card reader/punch
I finished the logic but keep flirting with yet another flaw in the Xilinx ISE toolchain. I get phantom errors in bitgen that I have too many bits for FDRI, which will go away, usually, if you do a Project Clean, restart the toolchain and run the generate again. Discussed quite a bit on various internet boards, as are the several other highly annoying flaws that waste design time.
Once I have a good generate I will fire up the system for the first test of the 1442 function. This will be more challenging from a testbed standpoint because it takes more hand toggled code to drive a 1442 properly. There are interrupts on level 0 for every column to which I must quickly respond with the XIO Read, as well as on level 4 for the completion of the card. I think I am ready.
I powered up and ran a test. It didn't work properly but that is not surprising because my hand code is still funky. I found some errors in my IOCC formats, for example. It will be hard to single step through the code to check it. With a 1442, there is very tight timing required to issue the XIO Read after each int on level 0.
If I tried to run the code in single instruction mode, a real 1442 reader would throw an error as the Read wasn't done fast enough. My virtual reader won't throw an error but it inexorably advanced through the columns triggering IL0 even if the Read didn't happen, so if I ran in SI mode it would not capture any card data.
I saw no response to the XIO Control with the bits to command a Start Read. I looked through the FPGA logic and found some code I thought was cleverly handling the case when the real 1442 adapter is live, but it wasn't. Worse, I forgot to tie down the 1442 adapter so that it was trying to respond to the XIO. I ran out of time for testing today but know what I need to do tomorrow - some diagnostic indications in the fpga and Python to help track what is occurring, once I have the jumper in place to disable the 1130's 1442 circuitry.
Implementing physical plotter (1627 equivalent)
I began by testing my interface electronics for the plotter, intended to allow the Strobe model 100 to act the same as a 1627. Something was not working correctly, however the movement buttons themselves work properly. This suggested the level shifter chip, since that is the main unit that sits between the input connector and the remaining circuitry that seems to be working properly. It was time to do some diagnostics.
This turned out to be solely an issue of bad connectors, a weakness of some of my project work. I was able to remove the connectors and validated I can drive the plotter left, right, up, and down as well lift or lower the pen to the paper. The plotter will be one of the devices that has its signals driven through a high speed link to another FPGA board which
I believe I have correct logic in the fpga matching the inboard adapter that IBM would install in 1130 systems if they came with a plotter. Mine does not, but the SAC Interface box will stand in for that logic. This will be the first thing I connect once my 1442 adapter is working solidly.